5 results about "Layout" patented technology

The invention discloses a knowledge graph visual editing and persistence implementation method and system architecture. According to the method, persistence of a knowledge graph editing result is allowed to be achieved based on a specific visual knowledge graph layout file, SPARQL query and visual interactive editing are supported, and the editing result can be persisted into a universal knowledgegraph file or a visual graph layout file defined by the invention. The system architecture mainly comprises a foreground visualization map interaction module and a background map database managementmodule. According to the method, the semantic relationship between entities described in a structured manner in the knowledge graph is visually expressed by using a visualization technology; Meanwhile, the layout file of the visual knowledge graph is defined, so that a user can conveniently store and recover a visual result. According to the invention, support can be provided for realizing efficient communication and intuitive display in related work of the knowledge graph.

The invention relates to an on-chip cache design method for memory stack compilation and layout collaboration and an on-chip cache. The method comprises the following steps: performing pre-layout planning on bonding logic to obtain a layout area, marking the layout area as a layout area, selecting a convergent point of a memory bank in the layout area, taking the convergent point as a reference point for calculating the distance from the memory bank to the bonding logic, selecting a position closest to the convergent point in a non-layout area, and taking the position as a reference point for calculating the distance from the memory bank to the bonding logic. And calculating the time sequence requirement of the current memory bank at the layout position according to the distance between the layout position and the rendezvous point, performing exhaustive compiling on the current memory bank to obtain a candidate compiling configuration set of the current memory bank, and selecting compiling configuration meeting the time sequence requirement in the set. By adopting the method, the position information of the memory bank can be considered while the memory bank is compiled, so that the time sequence requirement of the memory bank compiling can be accurately formulated, and the memory bank with the speed meeting the requirement and the optimal power consumption can be compiled.

The invention discloses a method for verifying the connection sequence of a signal line and a power line. The method comprises the following steps: exporting an integrated circuit layout to a DEF file and a GDS file; extracting effective information to a database X by utilizing the DEF file; automatic verification is carried out, and an error result is output; and correcting the error result, and returning to the above steps until no error result is output. According to the method, the connection sequence of the signal line and the power line of the large-scale integrated circuit can be verified, and the verification accuracy and efficiency are effectively improved.

The invention discloses a VUE-based componentization page development method, apparatus and device, and a storage medium, and belongs to the technical field of webpage development, the method comprises the following steps: before actual page development, obtaining a preset development demand of a page development project, and determining and constructing according to the preset development demand to obtain a target component; and when a Vue.js open source framework is used for designing an actual page in actual page development, selecting the target component conforming to the actual page, calling a target method in the target component, and performing componentized page development. According to the method, the components are constructed by adopting a modularization thought, the layout mode of the VUE is reserved, page layout is quickly carried out, various tool libraries are realized in combination with service requirements, the calling process of the tool libraries is simplified, a unified standard external interface is created, a unified coding specification is achieved, maintenance and management are facilitated, and finally the efficiency of VUE page development is improved.

The invention provides a page layout adjustment method and device, electronic equipment, a storage medium and a computer program product, and relates to the technical field of computers, in particular to the technical field of mobile terminal application programs. The method comprises the steps of obtaining a page root layout constructed based on a preset layout mode; wherein in the preset layout mode, the limiting dimension used for limiting the position of the page node is larger than the preset dimension; and removing at least one target node in the target page through the page root layout, and determining a first target dependency relationship of parallel nodes of the target node and a second target dependency relationship of child nodes of the target node to form a new page layout of the target page. By utilizing the page root layout, the nodes in the target page can be effectively deleted, and the dependency relationship of the nodes related to the deleted nodes can be accurately rewritten, so that the depth level of the existing page is effectively reduced, and the page rendering efficiency and the user experience are improved.