On-chip cache design method with memory stack compilation and layout collaboration and on-chip cache

The invention relates to an on-chip cache design method for memory stack compilation and layout collaboration and an on-chip cache. The method comprises the following steps: performing pre-layout planning on bonding logic to obtain a layout area, marking the layout area as a layout area, selecting a convergent point of a memory bank in the layout area, taking the convergent point as a reference point for calculating the distance from the memory bank to the bonding logic, selecting a position closest to the convergent point in a non-layout area, and taking the position as a reference point for calculating the distance from the memory bank to the bonding logic. And calculating the time sequence requirement of the current memory bank at the layout position according to the distance between the layout position and the rendezvous point, performing exhaustive compiling on the current memory bank to obtain a candidate compiling configuration set of the current memory bank, and selecting compiling configuration meeting the time sequence requirement in the set. By adopting the method, the position information of the memory bank can be considered while the memory bank is compiled, so that the time sequence requirement of the memory bank compiling can be accurately formulated, and the memory bank with the speed meeting the requirement and the optimal power consumption can be compiled.