Pipelined analog-digital converter

The present invention relates to a pipelined analog-digital converter, including a plurality of sub pipelined stages for implementing analog-to-digital conversion and allowance amplification to input analog signals; a time-delay synchronization register for implementing time-delay alignment to output digital codes from each pipelined stage; a digital correction module for receiving output digital codes from the synchronization register, and implementing bit shift addition to the output digital codes to obtain digital output codes of the analog-digital converter; a dynamic bias circuit for adjusting the bias level of the operational amplifier of each sub pipelined stage according to the frequency of sampling clocks to each sub pipelines stage; and a built-in band-gap reference source circuit for generating a reference voltage source of the dynamic bias circuit, thus the ''excess'' of the operational amplifier quantity for meeting the built-up time of a highest sampling frequency may be avoided, and an amplifying power will be reduced accordingly relative to a lower sampling frequency, thereby the power consumption of the analog-digital converter will be saved integrally.