Method for preparing metal pattern for fin field effect transistor

A fin field effect and metal pattern technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of affecting device performance and the effect of the connection between the metal layer zero and the fin layer, etc. The effect of large in-line process window, improved connection performance, improved device yield and reliability

Active Publication Date: 2017-06-06
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technology allows for better control over how well an integrated circuit (IC) chip operates when it's being designed or fabricated. By reversely etched lines at specific locations along certain directions within each channel region of the IC chip, we can improve its quality and reduce defective chips during production.

Problems solved by technology

This patented technical problem addressed by this patents relates to how to enhance the quality of Metal Layer Zero during fabricating processes for advanced semiconductor devices without causing issues like poor connections due to shorter lines caused by insufficient space between certain parts of the structure being worked on.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for preparing metal pattern for fin field effect transistor
  • Method for preparing metal pattern for fin field effect transistor
  • Method for preparing metal pattern for fin field effect transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0031] The following is attached Figure 1-13 The present invention will be described in further detail with specific examples. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the present embodiment.

[0032] For the preparation method of a fin field effect transistor metal pattern in this embodiment, please refer to figure 1 , including:

[0033] Step 01: See Figure 2~4 , providing a target pattern layout of a metal layer pat

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a method for preparing a metal pattern for a fin field effect transistor. The method comprises steps of: providing a target pattern layout of a metal layer pattern, inverting and then splitting a target pattern in the target pattern layout into a line layer pattern layout and a line end cutting layer pattern layout; providing a substrate layer having a fin layer and a gate layer; depositing a dielectric layer and a first hard mask layer on the substrate; etching a line layer pattern in the first hard mask layer by using the line layer pattern layout and a lithography and etching process; cutting the line end of a corresponding line layer pattern in the first hard mask layer by using the line end cutting layer pattern layout and the lithography and etching process; depositing a second hard mask layer on the line layer pattern and the exposed dielectric layer; removing the line layer pattern of the first hard mask layer and retaining the second hard mask layer; etching the dielectric layer by using the second hard mask layer as a mask, and forming a trench pattern in the dielectric layer; filling the trench pattern with metal and planarizing the metal surface to form the metal pattern.

Description

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products