7 results about "Memory address" patented technology

A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

The invention provides a file writing-in method of a SD (Secure Digital) card. The file writing-in process relates to a one-step DMA (Direct Memory Access) transmission process of wiring file data into a continuous physical cluster of the SD card from a discontinuous memory address. The method comprises the steps of: configuring first file transmission information, wherein the first file transmission information comprises initial addresses of multiple sections of file data in the memory and the information of the continuous physical cluster in the SD card; and sequentially reading data with corresponding length from the multiple sections of initial addresses of the memory, and continuously writing the data into the continuous physical cluster of the SD card. The invention can improve the direct memory access speed of the SD card and reduce the resource occupation of CPU (Central Processing Unit).

The invention discloses a binary-based system for detecting a memory modifying attack and positioning a bug, which comprises a code converting unit, a basic block data dependency relation recording unit, a code inserting unit and a bug positioning unit, wherein the code converting unit is used for converting x86 binary codes into VEX in the form of Valgrind intermediate codes; the code inserting unit comprises a color transmission code inserting part, an attack detecting code inserting part and a memory pollution command recording code inserting part, is used for dynamic staining analysis and can effectively detect the abnormal condition of memory data with the implementation of a program and record a writing command of a polluted memory; and the bug positioning unit comprises a modified memory address positioning part and a memory modifying command positioning part and is used for finding a memory address modified by an outer input and finding the address of the writing command modifying the memory to complete final positioning. The binary-based system can effectively detect the memory modifying attack and position the bug accurately.

A non-volatile memory device includes a control circuit configured to perform a block erase operation including a block erase cycle and an erase verify cycle on a block of memory cells. The control circuit is configured to perform the erase verify cycle by storing a last verify address for each sector of the block of memory cells, verifying each memory cell in a sector starting from the last verify address for the sector until a memory cell has failed erase verification in that sector, storing the memory cell address of the failed memory cell as the last verify address for that sector, skipping the erase verification for the remaining memory cells in that sector, and continuing the erase verify cycle at a last verify address for the next sector.

A light amount control device that controls an amount of light acquired from a light source provided in an image display apparatus includes: a pulse generator; an operation processing portion for light amount control that outputs a transfer start signal at timing when the amount of light is controlled; a data setting circuit that is provided outside the operation processing portion and that stores data, in which various kinds of signals instructing the operation processing portion to set transfer data beforehand are set, in a memory; an address generator that is provided outside the operation processing portion and that sets an address in response to the transfer start signal output from the operation processing portion; a memory that is a main component included in the pulse generator and that outputs data on the basis of a memory address generated by the address generator; a pulse driven body whose operation direction and speed are determined by a pulse signal formed by data output from the memory and which is driven by a pulse; an actuator connected to the pulse driven body; and an opening capable of adjusting the amount of transmitted light according to an operation of the actuator inserted in an emission path of the light source.

A method of operating a processor including performing successive read cycles from an instruction cache array and a line buffer array including providing sequential memory addresses, detecting a read hit in the line buffer array, and performing a zero clock retire while performing successive read cycles. The zero clock retire includes switching the instruction cache array from a read cycle to a write cycle for one cycle, selecting a line buffer and providing a cache line stored in the selected line buffer to be stored into the instruction cache array at an address stored in the selected line buffer, and bypassing a sequential memory address being provided to the instruction cache array during the zero clock retire. If the bypassed address missed the line buffer array, the bypassed address may be replayed with a slight time penalty, which is outweighed by the time savings of zero clock retires.

Disclosed are systems and methods for enabling secure execution of code in hypervisor mode. An exemplary method comprises: loading a hypervisor configured to check integrity of protected virtual memory pages; loading a trusted program configured to make hypercalls to the hypervisor; making by the trusted program a first hypercall to the hypervisor; responsive to the first hypercall, generating by the hypervisor a token, which is used by the hypervisor to identify the trusted program during subsequent hypercalls; allocating a memory page for storing the token and a memory address of the hypervisor; and returning the allocated memory page address to the trusted program.