Semiconductor device manufacture method

A device manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of good roughness and guaranteed performance

Active Publication Date: 2014-03-26
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing gate-last process still has difficulties in the following problems, such as the formation of ultra-thin lines (below 45nm), the precise control

Method used

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Example Embodiment

[0027] Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

[0028] The invention provides a semiconductor device manufacturing method, in particular to a dummy gate manufacturing method in a gate-last process, which overcomes some difficulties in the existing gate-last process. Below, see attached Figure 1-8 , the semiconductor device manufacturing method provided by the present invention will be described in detail.

[0029] First, see attached figure 1 A dummy gate oxide layer 11 and a dummy gate material layer 12 are sequentially formed on the semiconductor substrate 10 . Wherein, in this embodiment, a single c

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Abstract

The invention provides a dummy structure manufacture method. The method comprises the following steps: forming an ONO (oxide-nitride-oxynitride) structure and a top amorphous silicon layer on a dummy gate material layer; etching the ONO structure by using the patterned top amorphous silicon layer as mask which can precisely control the size and profile morphology of the ONO structure and control the etching rate and thickness of each layer of the ONO structure, so that the ONO structure becomes the desired mask of the dummy gate material layer; and etching the dummy gate material layer by using the ONO structure as mask to realize precise pattern transfer, so that the key dimension and profile morphology of a dummy gate can be controlled precisely and the subsequently formed metal gate has good roughness, thereby ensuring the performance and stability of the device.

Description

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Claims

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Application Information

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Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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