Transistor and formation method thereof

A transistor and topography technology, applied in the manufacture of transistors, semiconductor devices, semiconductor/solid-state devices, etc., can solve the problems of large leakage current of transistors, difficult to control transistor formation process, poor reliability, etc., to reduce the gate resistivity, Superior performance and high reliability

Active Publication Date: 2015-01-21
SEMICON MFG INT (SHANGHAI) CORP
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AI Technical Summary

Problems solved by technology

[0004] Although the introduction of a high-k metal gate can reduce the leakage current of the transistor to a certain extent, the problems of large l

Method used

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Example Embodiment

[0033] It can be known from the background technology that the prior art process for forming transistors has problems such as low reliability and large leakage current.

[0034] To this end, the transistor formation process is studied and found that the transistor formation process includes the following steps, please refer to figure 1 : Step S1, providing a semiconductor substrate; step S2, sequentially forming a gate dielectric layer, a barrier layer on the surface of the gate dielectric layer, and a sacrificial layer on the surface of the barrier layer on the surface of the semiconductor substrate; step S3, on the semiconductor substrate An interlayer dielectric layer is formed on the bottom surface, and the surface of the interlayer dielectric layer is flush with the top of the sacrificial layer; step S4, the sacrificial layer is removed to form a groove; step S5, a covering barrier layer is formed in the groove and The surface of the metal layer filled with the groove is flush w

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Abstract

Provided is a transistor and a formation method thereof. The formation method of the transistor include: providing a semiconductor substrate; successively forming, on the surface of the semiconductor substrate, a gate dielectric layer, a first barrier layer on the surface of the gate dielectric layer, and a sacrificial layer on the surface of the first barrier layer; forming an interlayer dielectric layer on the surface of the semiconductor substrate, wherein the surface of the interlayer dielectric layer is aligned to the top of the sacrificial layer; removing the sacrificial layer to form a slot; forming a second barrier layer, which covers the first barrier layer, in the slot, wherein the morphology of the second barrier layer and morphology of the first barrier layer on which the sacrificial layer has been removed are in complementation; forming a metal layer fully filling the slot on the surface of the second barrier layer, wherein the surface of the metal layer is aligned to the top of the interlayer dielectric layer. This invention reduces the leakage current of the gate of the transistor and improves the reliability and electrical properties of the transistor.

Description

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Claims

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Application Information

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Owner SEMICON MFG INT (SHANGHAI) CORP
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