System-grade packaged chip, preparation method thereof and equipment comprising system-grade packaged chip

A system-in-package and chip technology, applied in the field of microelectronics, can solve problems such as difficulty in meeting the needs of the Internet of Things

Inactive Publication Date: 2016-11-16
MIDEA SMART TECH CO LTD +1
View PDF8 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The technical effect that this new technology has been designed for was its ability to improve upon existing systems by adding certain improvements or modifications without affecting their overall performance.

Problems solved by technology

This patented technical problem addressed in this patents relates to improving the efficiency and accuracy of communications over internet of thing systems due to limited space available within these systems. Current methods have limitations including slow response times caused by long distances from signal sources like servers to clients' computers, which makes them vulnerable against attacks made during physical access. To address this issue, there exists a solution called Silicon Plane Networking (SPN).

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • System-grade packaged chip, preparation method thereof and equipment comprising system-grade packaged chip
  • System-grade packaged chip, preparation method thereof and equipment comprising system-grade packaged chip
  • System-grade packaged chip, preparation method thereof and equipment comprising system-grade packaged chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0046] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0047] figure 2 A block diagram of a SiP module provided for an embodiment of the present invention. Such as figure 2 As shown, the SiP module provided by an embodiment of the present invention includes: a microcontroller processing unit (Mirco Controller Unit; MCU) 200, a peripheral interface 210, and a system bus unit 201, and the microcontroller processing unit 200 is connected to the peripheral interface 210 is connected via the system bus unit 201.

[0048] In this embodiment, the MAC 200 may use an ARM Cortex-M4 processor, which is developed on the basis of the Cortex-M3 core, and its performance is 20% higher than that of the Cortex-M3. Newly added flo

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to the field of microelectronics, and discloses a system-grade packaged chip, equipment comprising the system-grade packaged chip, and a preparation method of the system-grade packaged chip. The system-grade packaged chip comprises the components of a microcontroller processing unit; a peripheral interface; and a system bus unit, wherein the microcontroller processing unit is connected with the peripheral interface through the system bus unit. According to the system-grade packaged chip, through packaging the system bus unit and the peripheral interface into the system-grade packaged chip, accessing of various peripheral devices into an SiP module can be facilitated. Furthermore utilization of the system bus unit can improve data throughput, and expansion of the system-grade packaged chip is facilitated.

Description

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Owner MIDEA SMART TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap