Semi-floating gate memory and preparation method thereof

A semi-floating gate and memory technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as reducing chip integration density

Active Publication Date: 2020-07-31
FUDAN UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in the existing planar semi-floating gate memory devices, the tunneling transistor is located between the floating gate and the drain, wh

Method used

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  • Semi-floating gate memory and preparation method thereof
  • Semi-floating gate memory and preparation method thereof
  • Semi-floating gate memory and preparation method thereof

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Embodiment Construction

[0024] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific The examples are only used to explain the present invention, not to limit the present invention. The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0025] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical" and "horizontal" are based on the orientation or positional relationshi

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Abstract

The invention discloses a semi-floating gate memory and a preparation method thereof. The semi-floating gate memory includes: a semiconductor substrate having a first doping type; a semi-floating gatewell region which has a second doping type and is positioned in the upper layer region of the semiconductor substrate; a U-shaped groove which penetrates through the semi-floating gate well region, and the bottom of the U-shaped groove is located at the lower boundary of the semi-floating gate well region; a first gate dielectric layer which covers the surface of the U-shaped groove; the floatinggate covers the first gate dielectric layer and forms a convex shape with a high middle part and two low sides; a tunneling transistor channel layer which covers the upper surface of the middle bulgeof the floating gate; second gate dielectric layers which are formed on the two sides of the tunneling transistor channel layer and extend to cover the surface of the floating gate, and the control gate covers the second gate dielectric layers and the upper surface of the tunneling transistor channel layer; gate side walls which are positioned on the two sides of the first gate stack and the second gate stack; and a source electrode and a drain electrode which are formed in the semi-floating gate well region and are positioned on the two sides of the first gate stack layer and the second gatestack layer.

Description

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Claims

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Application Information

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Owner FUDAN UNIV
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