Semiconductor memory device

Inactive Publication Date: 2008-10-02
LONGITUDE SEMICON S A R L
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011]That is, an object of the invention is to provide a control signal generator that not only adjusts the operation cycle time of

Problems solved by technology

However, in this method of generating timing in a column cycle using the access time, the following problem occurs.
Conversely, as a chip with bad performance is operated at the similar r

Method used

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  • Semiconductor memory device
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  • Semiconductor memory device

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Embodiment Construction

[0042]Referring to the drawings, embodiments of the invention will be described in detail below.

[0043]A circuit element forming each block in the embodiments is not particularly limited, however, the circuit element is formed on one semiconductor substrate made of monocrystalline silicon and others. A metal oxide semiconductor field effect transistor (MOSFET) without an arrow denotes N-type MOSFET (NMOSFET) and is distinguished from P-type MOSFET (PMOSFET) with an arrow. The MOSFET will be briefly called MOS below. However, the invention is not limited to only a field effect transistor including an oxide insulating film provided between a metal gate and a semiconductor layer and is applied to a circuit using general FET such as a metal insulator semiconductor field effect transistor (MISFET).

[0044]FIG. 1 shows the embodiment of the invention. FIG. 1 shows an example of the configuration of a timing control circuit for controlling the timing of column operation in a read command for a d

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Abstract

The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

Description

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Claims

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Application Information

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Owner LONGITUDE SEMICON S A R L
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