Semiconductor integrated circuit controlling output impedance and slew rate
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[0061]FIG. 1 is a schematic circuit diagram showing one embodiment of output buffers provided in a semiconductor integrated circuit according to the present invention. Output buffers 1 of this embodiment are directed to an output circuit of an open drain form. The output buffers 1 comprise plural N-channel output MOSFETs 100-122. These output MOSFETs 100-122 are connected in parallel so that their drains are commonly connected to an output terminal DQ and their sources are applied with a ground potential of the circuit. The output MOSFETs 100-122, to explain them more precisely, are nine MOSFETs 100-102, 110-112, and 120-122 and they are arranged in a matrix with three rows and three columns. Though there is no particular limitation, the output nine MOSFETs 100-122 are formed to be equal to each other in on-state resistance value, which is, e.g., 3*R (=3×R).
[0062] An output prebuffer 3 is disposed correspondingly to each of the above-mentioned output MOSFETs 100-122. The output prebuf
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