Semiconductor integrated circuit controlling output impedance and slew rate

Active Publication Date: 2006-11-16
RENESAS ELECTRONICS CORP
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  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Benefits of technology

[0010] An object of the present invention is to provide a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. Another object of the present invention is to provide a semiconductor integrated circuit that makes an impedance ratio constant in any output voltages regardless of a setting value. Another object of the present invention is to provide a semiconductor integrated circuit that includes an output circuit that keeps a slew rate quantity constant as long as impedance is constant, even if combinations of MOSFETs to set impedance to a setting value change. Another object of the present invention is to provide a semiconductor integrated circuit that includes an output circuit and an input circuit that are highly integrated. Another object of the present invention is to provide an easy-to-use semiconductor integrated circuit that can increase a data transfer rate on a system. The above-mentioned and other objects and novel characteristics of the present invention will become apparent from the description of this specification and the accompanying drawings.
[0011] A typical disclosure of the invention is summarized in brief as follows. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on i

Problems solved by technology

There is a problem in that this parasitic capacitance increases reflection noise in signal transfer.
Therefore, there is a problem in that, when manufacturing process and operating environment ch

Method used

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Example

[0061]FIG. 1 is a schematic circuit diagram showing one embodiment of output buffers provided in a semiconductor integrated circuit according to the present invention. Output buffers 1 of this embodiment are directed to an output circuit of an open drain form. The output buffers 1 comprise plural N-channel output MOSFETs 100-122. These output MOSFETs 100-122 are connected in parallel so that their drains are commonly connected to an output terminal DQ and their sources are applied with a ground potential of the circuit. The output MOSFETs 100-122, to explain them more precisely, are nine MOSFETs 100-102, 110-112, and 120-122 and they are arranged in a matrix with three rows and three columns. Though there is no particular limitation, the output nine MOSFETs 100-122 are formed to be equal to each other in on-state resistance value, which is, e.g., 3*R (=3×R).

[0062] An output prebuffer 3 is disposed correspondingly to each of the above-mentioned output MOSFETs 100-122. The output prebuf

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Abstract

The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.

Description

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Claims

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Application Information

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Owner RENESAS ELECTRONICS CORP
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