Memory Element and Semiconductor Device, and Method for Manufacturing the Same

Embodiment 1

[0093]This embodiment will describe a structure of the passive matrix memory device shown in Embodiment Mode 2 and a method for writing data therein.

[0094]In FIG. 5A a word line is Wn (1≦n≦y), and a bit line is Bm (1≦m≦x).

[0095]FIG. 5A shows a structure of a memory device of the present invention. A memory device 5008 of the present invention has a column decoder 5001, a row decoder 5002, a reading circuit 5004, a writing circuit 5005, a selector 5003, and a memory cell array 22. The memory cell array 22 includes a plurality of memory cells 21.

[0096]Each memory cell 21 has a memory element 80.

[0097]In the present invention, a bit line (first conductive layer) and a word line electrode (second conductive layer) connected to a word line are formed over a same plane as shown in Embodiment Mode 2. The memory element 80 has a word line electrode, a bit line, and a layer containing conductive fine particles between the word line electrode and the bit line.

[0098]Note that a struct

Embodiment 2

[0115]This embodiment will describe a structure of the active matrix memory device shown in Embodiment Mode 3 and a method for writing data therein using an equivalent circuit shown in FIGS. 7A and 7B.

[0116]An example of a structure of a memory device described in this embodiment has a column decoder 801, a row decoder 802, a reading circuit 804, a writing circuit 805, a selector 803, and a memory cell array 822. The memory cell array 822 includes a bit line Bm (1≦m≦x), a word line Wn (1≦n≦y), and x×y memory cells 821 at intersection portions of the bit line and the word line.

[0117]The memory cell 821 has a first wiring which forms a bit line Bx (1≦x≦m), a second wiring which forms a word line Wy (1≦y≦n), a transistor 840, and a memory element 841. The memory element 841 has a structure in which a layer containing conductive fine particles is interposed between a pair of conductive layers which are arranged in parallel, as the memory element shown in Embodiment Mode 3. Note

Embodiment 3

[0132]A structure of a semiconductor device will be described with reference to FIG. 8. As shown in FIG. 8, a semiconductor device 1520 according to the present invention has a function of non-contact communication of data, and includes a power supply circuit 1511, a clock generating circuit 1512, a data demodulation / modulation circuit 1513, a control circuit 1514 for controlling other circuits, an interface circuit 1515, a memory circuit 1516, a data bus 1517, an antenna (antenna coil) 1518, a sensor 1523a , and a sensor circuit 1523b.

[0133]The power supply circuit 1511 generates various kinds of power supply voltage to be supplied to each circuit inside the semiconductor device 1520, based on an AC signal inputted from the antenna 1518. The clock generating circuit 1512 generates various kinds of clock signals to be supplied to each circuit inside the semiconductor device 1520, based on the AC signal inputted from the antenna 1518. The data demodulation / modulation ci