3 results about "Shallow trench isolation" patented technology

Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

The invention relates to a preparation method of a semiconductor device and the semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate which comprises a shallow trench and an active region; forming an oxygen-containing layer on the exposed outer surfaces of the shallow trench and the active region; filling a first isolation layer with a set height in the shallow trench of which the surface comprises the oxygen-containing layer, wherein the set height is lower than the height of the active region; forming an etching stop layer on the upper surface of the first isolation layer; filling a second isolation layer on the etching stop layer in the shallow trench to form a shallow trench isolation structure; and etchingthe active region and the shallow trench isolation structure etched to form a word line trench, and the bottom of the word line trench in the shallow trench isolation structure is higher than a set height. According to the preparation method disclosed by the invention, the etching stop layer can be utilized to control the depth of the word line groove in the shallow groove isolation structure, so that the depth of the word line groove is kept consistent with the depth of the word line groove in the active region as much as possible.

The invention provides a method for preparing a 3D surrounding gate MOS transistor, comprising the steps of: forming an N-type well and a P-type well isolated by a shallow trench isolation structure on a silicon substrate; Silicon nanowires are grown on the region to form NPN nanowires and PNP nanowires respectively; after continuing to deposit an oxide isolation layer and planarize, remove the oxide isolation layer located in the middle; sequentially deposit the gate oxide layer and polysilicon , and after etching away the polysilicon located between the NPN nanowire and the PNP nanowire, deposit an oxide isolation layer; remove part of the oxide isolation layer to expose part of the polysilicon covering the NPN nanowire and the PNP nanowire, and The exposed polysilicon is removed; after the oxide isolation layer is deposited again, the source, drain and gate are prepared to form a MOS transistor. The method is easy to operate, improves the control ability of the gate to the channel and improves the performance of the device.