Semiconductor element and wafer level chip size package having it
A wafer-level chip and size packaging technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device parts, electrical components, etc., can solve the problem of not fully avoiding the overall bending of CSP501, so as to avoid bending, increase the total area, and improve freedom. degree of effect
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[0164] The present invention will now be further specifically described by way of examples with reference to the accompanying drawings.
[0165] 1. The first embodiment
[0166] will now refer to figure 1 , 2 , 3, 4A-4F and 5 to describe the semiconductor device according to the first embodiment of the present invention. Such as figure 1 and 2 As shown, the semiconductor device 1 includes: a semiconductor chip 3 having a rectangular plate-like shape in a plan view; an insulating layer 5 (used as a first insulating layer) formed on a surface 3a of the semiconductor chip 3; A plurality of connecting electrodes 7 and radiating electrodes 9 provided on it; a plurality of wiring portions 11, 13 and 15 formed on the surface 5a of the insulating layer 5 to establish mutual connection between the semiconductor chip 3 and the connecting electrodes 7 or radiating electrodes 9 and a molding resin 17 (used as a second insulating layer) that covers the surface 5a of the insulating l...
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