Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

a semiconductor device and silicon carbide technology, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problems of forward characteristics degrading and the resistance of the nsup>/sup>-type drift layer increasing

Active Publication Date: 2019-08-01
FUJI ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

This patent describes a method for making a special type of material called silicon carbide (SiC). It consists of two layers: a donor layer made of silicon carbide and another layer made of silicon carbide. These layers are placed next to each other when they form a specific pattern. By controlling the ratio between these two layers, it can create different types of materials like SiC devices or transistors.

Problems solved by technology

This patent describes a method for improving the performance of a Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) without losing their ability to operate properly. One solution involves adding certain elements called n+-type buffer layers onto the surface of the drift layer before epitaxy growth of the drift layer. These buffer layers help improve the quality of the crystal lattice and reduce defect formation during epitaxy growth. Additionally, there can also include a process called self-alignment to further enhance the performance of the MOSFETs. By forming these buffers and combining them with other materials like nitrogen or phosphorus, the specific elements in the MOSFETs can be prevented from mixing into the drift layer during epitaxy growth.

Method used

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  • Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
  • Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
  • Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

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first embodiment

[0042]The silicon carbide semiconductor device depicted in FIG. 1 is a pin diode in which silicon carbide layers respectively constituting the n+-type buffer layer (or first first-conductivity-type epitaxial layer) 2, the n−-type drift layer 3, and the p+-type anode layer 4 are sequentially formed by epitaxial growth on a front surface of the n+-type starting substrate 1 that contains silicon carbide. An anode electrode 5 and a cathode electrode 6 are electrically connected to the p+-type anode layer 4 and a rear surface of the n+-type starting substrate 1 (or n+-type cathode layer), respectively.

[0043]For example, nitrogen (N) is introduced into the n+-type starting substrate 1 as an n-type dopant. An n-type impurity concentration (or nitrogen concentration) and a thickness t1 of the n+-type starting substrate 1, for example, may be about 5.0×1018 / cm3 and about 350 μm, respectively. In FIG. 1 and FIG. 3, introduction of nitrogen as a dopant is indicated as “N doped”.

[0044]The n+-ty

second embodiment

[0085]In the second embodiment, the n-type impurity concentration (or nitrogen concentration) in the n−-type drift layer 33 is set to be about 1×1015 / cm3 or less, thereby enabling high breakdown voltage. In particular, the n-type impurity concentration (or nitrogen concentration) and the thickness t3 of the n−-type drift layer 33, for example, may be set to be about 3×1014 / cm3 and about 150 μm, respectively, for a 13 kV pin diode. In this case, the n-type impurity concentration in the second part 32b of the n+-type buffer layer 32 is reduced, whereby auto-doping of the n-type impurity (or nitrogen) from the n+-type buffer layer 32 to the n−-type drift layer 33 at a high concentration may be suppressed during epitaxial growth of the n−-type drift layer 33.

[0086]The method of manufacturing a silicon carbide semiconductor device according to the second embodiment includes in the method of manufacturing a silicon carbide semiconductor device according to the first embodiment (refer to

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Abstract

On a front surface of an n+-type starting substrate containing silicon carbide, a pin diode is configured having silicon carbide layers constituting an n+-type buffer layer, an n−-type drift layer, and a p+-type anode layer sequentially formed by epitaxial growth. The n+-type buffer layer is formed by so-called co-doping of nitrogen and vanadium, which forms a recombination center, together with an n-type impurity. The n+-type buffer layer includes a first part disposed at a side of a second interface of the buffer layer with the substrate and a second part disposed at side of a first interface of the buffer layer with the drift layer. The vanadium concentration in the second part is lower than that in the first part. The vanadium concentration in the second part is at most one tenth of the maximum value Vmax of the vanadium concentration in the n+-type buffer layer.

Description

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Claims

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Application Information

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Owner FUJI ELECTRIC CO LTD
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