Semiconductor memory device

a memory device and semiconductor technology, applied in the direction of semiconductor devices, basic electric elements, electrical appliances, etc., can solve the problems of limited integration of 2d semiconductor devices, and achieve the effect of improving reliability

Active Publication Date: 2019-10-24
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention improves the reliability of semiconductor memories by adding certain features that enhance their performance.

Problems solved by technology

This patent describes how 3D semiconductors can improve their efficiency in terms of reducing production costs while maintaining good device performance. By creating tiny structures on both sides of each layer of the chip, it becomes possible to achieve this without requiring expensive equipment.

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

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Embodiment Construction

[0029]FIG. 1 is a schematic circuit diagram illustrating a cell array of a semiconductor memory device according to an exemplary embodiment of the present inventive concept.

[0030]Referring to FIG. 1, a semiconductor memory device may include a common source line CSL, a plurality of bit lines BL0 to BL2, and a plurality of cell strings CSTR provided between the common source line CSL and the plurality of bit lines BL0 to BL2.

[0031]The plurality of bit lines BL0 to BL2 may be two-dimensionally arranged and the plurality of cell strings CSTR may be connected in parallel to each of the plurality of bit lines BL0 to BL2 and connected to the common source line CSL. Thus, the cell strings CSTR may be two-dimensionally arranged on the common source line CSL or a substrate. The common source line CSL may be provided in plural, with the plurality of common source lines CSL supplied with the same voltage, or in some instances independently controlled and supplied with voltages different from each

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Abstract

A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.

Description

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Claims

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Application Information

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Owner SAMSUNG ELECTRONICS CO LTD
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