6 results about "Asymmetry" patented technology

A method and apparatus for LCL resonant converter control utilizing Asymmetric Voltage Cancellation is described. The methods to determine the optimal trajectory of the control variables are discussed. Practical implementations of sensing load parameters are included. Simple PI, PID and fuzzy logic controllers are included with AVC for achieving good transient response characteristics with output current regulation.

The invention relates to a lagging comparer, wherein it comprises current source I1, two input MOS tubes, three load MOS tubes, and lagging adjuster for adjusting the threshold value of comparer. When the input MOS tube is NMOS tube, the load MOS tube uses PMOS tube; the single threshold value of circuit is irrelative to the circuit element parameters, that one fixed input voltage of comparer can fix single threshold value; the inventive circuit has asymmetry positive feedback circuit to form the lagging circuit of lagging comparer, to generate threshold voltage and complete comparison. The invention also has positive feedback branch and output branch, MOS tube with static protection and resistance.

The invention provides a face symmetry plane obtaining method based on iterative mirroring and registration, and belongs to the field of computer vision. The face symmetry plane obtaining method comprises the following steps that (1) face data are acquired through 3D scanning, and a point cloud is smoothly scanned by a Gaussian filter; (2) the longitudinal axis is roughly estimated through PCA, the face is axially segmented to acquire slice contour, and the most symmetrical points are determined and the symmetry plane is solved; and (3) a new point cloud is generated by the symmetry plane point cloud, the point cloud and mirroring data are registered through ICP and registration iteration is performed and the symmetry plane is solved. The novel face symmetry plane obtaining method is put forward on the basis of the iterative mirroring and registration method so that the influence of the local asymmetry of the symmetrical object and the asymmetry caused in the scanning process can be effectively avoided and the obtained symmetry plane is enabled to be more accurate.

The invention belongs to the field of energy metering, and relates to a self-healing precision correction method for a supersonic heat energy metering device. The method comprises the following main technological steps: firstly carrying out the hardware configuration of the supersonic heat energy metering device; secondly selecting a conventional TG840 main control chip and a TDC-GP22 time chip; thirdly setting a conventional zero-returning algorithmic program of static zero time difference of the supersonic heat energy metering device in the chips; fourthly setting a conventional program which obtains time difference through a peak value and a minimum value in the main control and time chips; and finally carrying out the non-linear correction of the supersonic heat energy metering device through a function of self-healing correction of the metering device. The method effectively eliminate the impact on metering precision from the factors (physical asymmetry, time drift, pipe bubbles and on-site noise) of an electronic circuit, enables the metering device to be simple in the overall structure, and enables the time measurement precision to be high.

The invention discloses an MRAM (Magnetic Random Access Memory) sense amplifier capable of offsetting deviation. The MRAM read-out circuit is used as a post-amplifier of the MRAM read-out circuit, andcomprises NMOS tubes M0 and M1 with the same parameters, NMOS tubes M2 and M3 with the same parameters, PMOS tubes M4 and M5 with the same parameters, capacitors C0 and C1, and three same switches K1and K2; the drain electrode of the M2 is connected with the drain electrode of the M4, wherein the connection point is a point A; the grid of M2 is connected with the grid of M4, wherein the connection point is a point B; the drain of M3 is connected with the drain of M5, wherein the connection point is a point C; the grid of M3 is connected with the grid of M5, wherein the connection point is apoint D; the capacitor C0 is connected between the point B and the point C, and the capacitor C1 is connected between the point A and the point D. In the working stage, the capacitor C0 and the capacitor C1 counteract asymmetry of the read-out differential amplifier. A pair of capacitors is added on the basis of a common differential comparator, asymmetry of the differential amplifier can be counteracted, and meanwhile the area of the amplifier does not need to be large.