Position design of alignment marks

[0024] Please also refer to figure 2 as well as image 3 , figure 2 What is shown is an exploded schematic diagram of the three-dimensional structure of the position design of the non-zero layer alignment mark of the preferred embodiment of the present invention, and image 3 What is shown is a cross-sectional schematic diagram of the positional design of the non-zero layer alignment mark of the preferred embodiment of the present invention.

[0025] Depend on figure 2 and image 3 It can be seen that the alignment mark 208 is disposed in a planarized dielectric layer 206 on the semiconductor substrate 200, and the method for forming the alignment mark 208 is, for example, firstly forming several long lengths with similar positions in the dielectric layer 206. strip-shaped openings (not shown), and metal material is filled in the strip-shaped openings to form non-zero layer alignment marks composed of a plurality of metal lines. Usually, the alignment mark manufacturing p