Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit

[0013]Programmable logic devices exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs), complex programmable logic devices (CPLDs), and Field Programmable Gate Arrays (FPGAs) among others. Many PLDs have the types of embedded speed sensitive architectures that employ self-timed reference delay circuits used in the present invention.

[0014]After a PLD with an embedded asynchronous speed sensitive architecture has been manufactured, that PLD must be tested for operability. Part of that testing includes speed binning, the practice of identifying the fastest speed or clock frequency at which the device may be run. Typically, this testing will proceed by cycling through different clock speeds, slowest to fastest, to establish the fastest clock frequency at which the device will operate. The speed binning will result in a plur