Chip package

[0051] figure 1 It is a schematic cross-sectional view of a chip package according to the first embodiment of the present invention. Please refer to figure 1 , in this embodiment, the chip package 100 includes a carrier 110 having an opening 110a, a first chip 120, a plurality of bumps 130, a second chip 140, a plurality of bonding wires 150, a first adhesive layer 160 and an encapsulant 170 . The first chip 120 has a first active surface 120a and a first back surface 120b opposite to the first active surface 120a. The first chip 120 and the second chip 140 are disposed on the carrier 110 and located on two sides of the carrier 110 . The bumps 130 are disposed between the carrier 110 and the first active surface 120 a of the first chip 120 , and the first chip 120 is electrically connected to the carrier 110 through the bumps 130 . These bonding wires 150 are electrically connected to the carrier 110 and the second chip 140 , wherein each bonding wire 150 passes through th...