Self-aligned trench isolation method and semiconductor device fabricated using the same

[0028]Embodiments of the invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be through and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of the layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification.

[0029]FIGS. 9 to 15 are cross-sectional diagrams illustrating self-aligned trench isolation methods according to some embodiments of the invention and semiconductor memory devices fabricated using the same.

[0030]Referring to FIG. 9, a first gate insulating layer, a first lower gate conductive layer and a gate etching stopper layer are sequentially for