Signal processing unit

[0062]A structure of a signal processing unit of one embodiment of the present invention is described with reference to FIG. 1 and FIG. 2. FIG. 1 is a block diagram illustrating a structure of a signal processing unit 100 and a reading circuit 104 connected to the signal processing unit 100.

[0063]Note that a large scale integrated circuit (LSI) such as a CPU, a microprocessor, an image processing circuit, a digital signal processor (DSP), or a field programmable gate array (FPGA), and the like are included in the signal processing unit of the preset invention in its category.

[0064]The signal processing unit 100 includes a logic circuit 101 for performing a variety of processing based on data input, a power supply circuit 103 for supplying power to the logic circuit 101, and a storage circuit 102 for storing data processed in the logic circuit 101.

[0065]Further, the storage circuit 102 is connected to the reading circuit 104. The reading circuit 104 is supplied with power from a powe...

[0100]In this embodiment, a structure that is different from that in FIG. 1 is described with reference to FIG. 4.

[0101]A signal processing unit 150 illustrated in FIG. 4 has a structure that is similar to the signal processing unit 100 illustrated in FIG. 1 except the power supply circuit 103 is not provided. Power is supplied from a power supply circuit 151 to the signal processing unit 150 and the reading circuit 104 via a power distribution circuit 152.

[0102]The supply of power from the power supply circuit 151 to the logic circuit 101 and the supply of power from the power supply circuit 151 to the reading circuit 104 can be independently stopped by the power distribution circuit 152. The power distribution circuit 152 can supply plural levels of power in accordance with circuits connected to the power distribution circuit 152.

[0103]A plurality of power supply circuits are combined into one in such a way, so that a design of a semiconductor device is simple and the productivity...

[0104]In this embodiment, another example of a configuration of a storage circuit is described with reference to FIG. 5.

[0105]A storage circuit 200 illustrated in FIG. 5 includes a phase inverter 201, a phase inverter 202, the transistor 121 that includes an oxide semiconductor as a semiconductor layer in which a channel is formed, and the capacitor 122. Note that the storage circuit 200 may further include another circuit element such as a diode, a resistor, or an inductor, as needed.

[0106]Note that the capacitor 122 is not necessarily provided as long as the parasitic capacitance of the transistor or the like is actively utilized.

[0107]An output terminal (represented as “out” in the diagram) of the phase inverter 201 is electrically connected to one of a source and a drain of the transistor 121. The other of the source and the drain of the transistor 121 is electrically connected to one of a pair of electrodes of the capacitor 122 and an input terminal (represented as “in” in the ...