9 results about "Parasitic capacitance" patented technology

System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

The invention provides a pixel structure which comprises a plurality of pixel electrodes, a plurality of data lines and a plurality of scanning lines. The scanning lines are arranged at two opposite ends of the pixel electrodes respectively, the data lines are perpendicular to the scanning lines, each pixel electrode comprises at least two sub pixel areas, the data lines are positioned below the pixel electrodes and positioned at junctions of two adjacent sub pixel areas, and a plurality of gaps are formed at positions, where two sub pixel areas are intersected, of the pixel electrodes, align the data lines and are positioned above the data lines. The invention further provides a liquid crystal display. Overlap area between the data lines and the pixel electrodes above the data lines is reduced, so that parasitic capacitance between the data lines and the pixel electrodes is lowered, and vertical crosstalk in a grey-background white-frame picture can be improved.

The electrode for high-voltage in-situ impedance spectroscopy measurement of the present invention and its preparation method and application belong to the technical field of in-situ measurement of electrical quantities under high-voltage conditions. The electrode consists of an aluminum oxide protective layer (3) deposited on the surface of the diamond anvil (2) and a metal film electrode (1); the metal film electrode (1) is circular in the center of the anvil surface of the diamond anvil (2), Copper wire (5) is bonded to the metal film electrode (1) on the side of the diamond anvil (2); the metal spacer (4) is used as another electrode, forming an axisymmetric electrode together with the metal film electrode (1) system. Electrodes are prepared by magnetron sputtering, molybdenum coating, aluminum oxide deposition, photolithography and chemical corrosion. The invention solves the problems of electrode fixing and sample cavity insulation, and can ignore the influence of the parasitic capacitance and inductance of the system on the measurement results, making it possible to measure the material impedance spectrum in situ with the diamond anvil under high pressure.

A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

The invention belongs to the technical field of micro-electronics, particularly disclosing a nanowire MOS transistor and a preparation method thereof. The nanowire MOS transistor uses metallic nickel to serve as the drain and source diffusion material of III-V semiconductor nanowire and utilizes the nickel diffusion mechanism under high temperature to ensure that metallic nickel diffuses to III-V material; formed low-resistance Ni-III-V alloy serves as the drain and source diffusion material of the III-V semiconductor nanowire MOS pipe so as to realize ohmic contact between the drain and source material and channel material. The MOS transistor disclosed by the invention has the advantages of simple structure, convenient manufacture, small contact resistance and the like, can effectively lower the possibility of producing parasitic capacitance and effectively lowers the cut-off current of the MOS transistor. Meanwhile, the invention also discloses a preparation method of the nanowire MOS transistor, can effectively control the channel length of the MOS transistor so as to ensure that a semiconductor device has larger operating current.

The invention discloses an interlayer hole modeling method and an anti-single event effect analysis method and device, and a three-dimensional monolithic integrated circuit comprises a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an interlayer dielectric medium located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer. An interlayer hole is formed in an interlayer dielectric medium, and the method comprises the steps that the size of the interlayer hole, the resistivity of an interlayer hole material and the attribute of the interlayer dielectric medium are determined; constructing a parasitic resistance model of the interlayer hole based on the size of the interlayer hole and the resistivity of the interlayer hole material; and constructing a stray capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the attribute of the interlayer dielectric.