13 results about "Circuit design" patented technology

A method of input/output (I/O) assignment for a circuit design for a programmable logic device (PLD) can include determining I/O types for I/O objects specified by the circuit design, defining a plurality of virtual I/O bank-groups, wherein each virtual I/O bank-group includes at least one virtual I/O bank, and binding I/O objects of the circuit design into I/O groups according to the I/O types. A binary compatibility matrix can be created. The binary compatibility matrix can indicate the compatibility between the virtual I/O bank-groups and the I/O groups based upon the I/O types of I/O objects within each I/O group. A determination can be made as to whether a feasible solution exists for I/O assignment of the I/O objects of the circuit design according to a plurality of constraints and the binary compatibility matrix.

The invention discloses a low-power consumption bandwidth multiplication chopping stabilized operational amplifier based on an MOS (metal oxide semiconductor) device, which belongs to the field of design of analog integrated circuits. The low-power consumption bandwidth multiplication chopping stabilized operational amplifier comprises two frequency mixers, a shunt input stage, an intermediate stage for amplifying recovered current and a rail-to-rail output stage, wherein one frequency mixer is placed in front of an amplifier input stage, and the other frequency mixer is placed behind an amplifier output stage, thereby realizing the functions of raising frequency and reducing frequency of input signals; the shunt input stage is used for converting input voltage signals to current signals and forming small signal current in forward and backward directions; the intermediate stage for amplifying the recovered current comprises four low-voltage current mirrors and can realize the amplification of the recovered current; and the rail-to-rail output stage is used for realizing the rail-to-rail output of the signals. The low-power consumption bandwidth multiplication chopping stabilized operational amplifier has the capacity of improving bandwidth by nearly three times under the situation of not obviously increasing power consumption, and can reduce low-frequency 1/f noise, increase low-frequency gain, and reduce power consumption above one half while keeping the same bandwidth, the noise and other performances, thereby further improving the performances of the circuit.

The pin possesses three output ends A, B and C. An end through a clock signal strobe module is connected to the pin. B end through a high-level strobe module is connected to the pin. C end is leaded out directly from the pin. The said clock signal strobe module is composed of a 4 bits binary counter and a state clamping trigger. The high-level strobe module is composed of 32 frequency dividing circuit and a feedback state control circuit. Based on different signals provided for the pin from external, the multifunctional pin circuit provides different control electrical level for controlling other pins or internal circuits.

The present invention discloses a short circuit and detection dual-purpose device used for relay protection. The short circuit and detection dual-purpose device is characterized by comprising a cuboid operation box, wherein the operation box is equipped with a buckle-type opening-closing door, and a fuse placement fastening groove is arranged in the door; the operation box is additionally equipped with a circuit on-off selection switch, a circuit on-off indication lamp, a rotary switch, a voltage display meter, a first current display meter and a second current display meter, a wiring port is arranged on the side surface of the operation box, and a short circuit alarm circuit and a detection circuit are arranged inside the operation box. Compared with the prior art, the advantages of the present invention are that: the short circuit and detection dual-purpose device is simple and reliable in circuit design, the personal low-voltage electric shock caused by that the operation personnel touch a test wiring wrongly in a live wire manner and the damage of a relay protection tester and a protection device plug-in are avoided, the personal injury and the equipment damage caused by a wrong short circuit during a short circuit test process are avoided effectively, and the accuracy and the safety during the short circuit test are improved.

The invention discloses a charging control circuit of a low voltage power supply to a high voltage battery pack based on an adjustable battery pack series structure. The circuit design can perform charging control on each single battery (or single battery pack) via a breakover path for controlling a current, the multiple single batteries can be randomly and dynamically selected according to a voltage value of the low voltage power supply to be connected serially and added into a charging loop, and thus the low voltage power supply charges the high voltage battery pack. The active equalizationcapacity that has the same size with the charging current can be achieved for the single battery (or the single battery pack) that is not added into the serial bus. Via dynamic control, each single battery (or single battery pack) in the battery pack can be fully charged.

The invention relates to a DBC board layout method for reducing the parasitic inductance of GaN HEMT power module packaging, and belongs to the technical field of semiconductor packaging. The DBC board is pasted with components with circuit design layout, wherein the components include a GaN chip, an MOS chip, a gate resistor and a power terminal. The DBC board includes a source region, a drain region and a gate region, the GaN chip, the MOS chip, the gate resistor and the DBC board are welded by means of solder paste reflow, and the vacant space reserved among the GaN chip, the MOS chip, the gate resistor and the power terminal is clad copper on the DBC board. According to the invention, the DBC board is reasonably laid out, the parasitic inductance of the clad copper on the surface of the DBC board is improved, the loss caused by the overlarge parasitism of a GaN device in the packaging form at a high frequency is reduced, and the method for packaging the high-frequency GaN power module structure is realized.

The invention relates to an electric professional display device, in particular to an electric professional integrated circuit design display device. The technical problem is to provide an electric professional integrated circuit design display device capable of fixedly displaying integrated circuit design and keeping integrated circuit design clean. The technical scheme of the invention is as follows: an electric professional integrated circuit design display device comprises a placing frame, a leg, a support, an L-shaped rod, a return plate, a first placing plate, a second placing plate, a slot plate, a connecting plate, a card block, a sliding plate, a sliding sleeve and the like; The lower part of the left and right sides of the placing frame is connected with legs, the bottom of the legs is connected with supports, and the left and right sides of the front side of the placing frame are connected with L-shaped bars. The first placement groove of the invention can be moved downwardand matched with the second placement groove to fix the integrated circuit design, so that the teacher can conveniently teach the students, and the teacher does not need to hold the integrated circuitdesign high to display the students.

The invention relates to a multicolored fish tank. A light source lamp and a control module are arranged and fixed on a circuit board according to the correct circuit design in advance, the circuit board is arranged and fixed inside a base, a fixed switch and a socket are arranged in proper positions of the base, and a transparent fish tank is arranged and fixed right above the base.

Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.

The present invention discloses a BME technology-based wireless LED control system and method. The system comprises a PC terminal used for sending an RF data frame; a coordinator connected with the PC terminal and comprising a microcontroller in which a BME bit operation mechanism is arranged and a wireless transmission module is integrated; an LED terminal comprising a plurality of terminal nodes and an LED lattice screen, wherein the terminal nodes are connected with the coordinator via the wireless transmission module and receive the RF data frame sent by the PC terminal, and the LED lattice screen is connected with the terminal nodes separately. According to the present invention, the KW01 microcontroller is integrated with a wireless module, so that the circuit design is simple, the peripheral devices are few, and the hardware cost is saved. A wireless transmission mode facilitates the LED installation and facilitates wiring conveniently. By designing the format of a communication frame independently, the communication stability and accuracy are enhanced. By utilizing a bit operation engine technology to operate the GPIO external storage space, few codes are generated after compiling, especially an instruction cycle of program execution is reduced substantially.