Semiconductor device, semiconductor structure and manufacturing method of interconnection structure

A manufacturing method and interconnection structure technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of electromigration failure of interconnection structure, poor signal transmission effect, low product yield, etc. problems, to improve transmission performance, avoid voids, and ensure product quality

Inactive Publication Date: 2021-03-19
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technology describes methods for making connections within electronic components or structures with high conductance materials (such as copper). By removing certain areas on these surfaces beforehand, they become smaller but still have enough space to allow them to fill up without getting trapped by other things like another component's surface. These techniques help improve production efficiency and reduce defect rates caused by poorly filled openings. Additionally, this design prevents unwanted metallic deposits around specific parts of the circuitry, resulting in better reliability and reduced failure probability overtime.

Problems solved by technology

This patented technical problem addressed in this patents relates to improving the quality of interconnections during fabrication without leaving any unwanted residues behind due to insufficient deposit rates at certain areas caused by excessive electrostatic charge buildup from previous steps.

Method used

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  • Semiconductor device, semiconductor structure and manufacturing method of interconnection structure
  • Semiconductor device, semiconductor structure and manufacturing method of interconnection structure
  • Semiconductor device, semiconductor structure and manufacturing method of interconnection structure

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Embodiment Construction

[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0041] The features, structures or characteristics described above may be combined in any suitable manner in one or more embodiments and, where possible, the features discussed in the various embodiments are interchangeable. In the description above, numerous specific details are provided in order to give a thorough understanding of embodiments of the present application. However, those skilled in the art will appreciate that t

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Abstract

The invention discloses a semiconductor device, a semiconductor structure and a manufacturing method of an interconnection structure, belonging to the technical field of semiconductors. The manufacturing method of the interconnection structure comprises the steps that a barrier layer and a seed layer are sequentially formed on a dielectric layer with a groove, and the barrier layer and the seed layer are attached to the dielectric layer in a conformal mode; nitrogen ions are injected into the seed layer according to a preset angle to form a nitrogen-containing seed layer, and the nitrogen-containing seed layer is located on the top surface of the groove and extends towards the bottom of the groove along the two side walls of the groove; the nitrogen-containing seed layer is removed, a metal layer covering the barrier layer is formed, and the groove is filled with the metal layer; and the metal layer and the barrier layer on the top surface of the groove are removed, and planarization processing is performed on the metal layer in the groove to enable the metal layer in the groove to be flush with the surface of the dielectric layer on the top surface of the groove. According to themanufacturing method disclosed by the invention, cavities can be avoided, yield is improved, and meanwhile, the transmission performance of the interconnection structure and the semiconductor device can be improved.

Description

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Claims

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Application Information

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Owner CHANGXIN MEMORY TECH INC
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