9 results about "Semiconductor technology" patented technology

The invention provides a preparation method of a top gate metal oxide thin film transistor (TFT), belonging to the technical field of semiconductors. The method comprises the following steps: preparing a source/drain electrode; then preparing a metal oxide material; coating a photoresist on the surface of the metal oxide material and carrying out chemical mechanical polishing on the photoresist layer; processing the metal oxide which is not masked by the photoresist by annealing or plasmas; and finally stripping the photoresist and depositing a gate insulation layer material through magnetronsputtering and forming a gate through wet etching. The method has the following beneficial effects: reliable ohmic contact between the metal oxide thin film and the source/drain electrode can be formed by utilizing the characteristic that the metal oxide material can be converted into a conductor from a semiconductor after undergoing special processing.

The invention discloses an LED chip and a manufacturing method therefor, and belongs to the technical field of a semiconductor. The LED chip comprises a substrate, and an n type nitride semiconductor layer, a light emitting layer, a p type nitride semiconductor layer, a current barrier layer and a transparent conductive layer which are laminated on the substrate in sequence; a groove which extends to the n type nitride semiconductor layer is formed in the p type nitride semiconductor layer; a passivation layer is arranged on the n type nitride semiconductor layer, the side wall of the groove and the transparent conductive layer; a first through hole which extends to the p type nitride semiconductor layer is formed in the passivation layer on the transparent conductive layer; a p type electrode is arranged in the first through hole; a second through hole which extends to the n type nitride semiconductor layer is formed in the passivation layer on the n type nitride semiconductor layer; an n type electrode is arranged in the second through hole; and a plurality of third through holes which extend to the p type nitride semiconductor layer are formed in the current barrier layer. According to the LED chip, light rays emitted below the current barrier layer can pass through the third through holes to be emitted, so that light output and luminance can be improved.

The invention discloses a preparation method of a light emitting diode epitaxial wafer, and belongs to the technical field of a semiconductor. The preparation method comprises the steps of providing an AlN sapphire substrate; enabling a non-doped gallium nitride layer to be grown on the AlN sapphire substrate; enabling an N type gallium nitride layer to be grown on the non-doped gallium nitride layer; enabling a multi-quantum-well layer to be grown on the N type gallium nitride layer; enabling an electron barrier layer to be grown on the multi-quantum-well layer; and enabling a P type galliumnitride layer to be grown on the electron barrier layer, wherein the electron barrier layer is a P type doped aluminum gallium nitrogen layer; and the surface, for growing the P type gallium nitride layer, of the electron barrier layer is a nitrogen polarized surface. By setting the surface, with the P type gallium nitride layer, of the electron barrier layer into the nitrogen polarized surface, the contact between the electron barrier layer and the P type gallium nitride layer is closer due to the fact that the nitrogen polarized surface is more uneven in a concave and convex manner than themetal polarized surface, so that the ohmic contact resistance is low, the short channel effect is weak, hole injection can be promoted, the recombination efficiency of holes and electrons can be improved, and the luminous efficiency of the light emitting diode is improved.

The invention discloses the spot measurement equipment of a light emitting diode chip and belongs to the semiconductor technology field. The spot measurement equipment comprises a bearing device, an optical path conversion device and a light collection device, wherein the bearing device is used for bearing a light emitting diode chip; the optical path conversion device is arranged between the bearing device and the light emitting diode chip and is used for reflecting light emitted to the bearing device by the light emitting diode chip to the light emitting surface of the light emitting diode chip; and the light collection device is arranged toward the light emitting surface of the light emitting diode chip and is used for detecting the optical parameters of the light emitting diode chip. The spot measurement equipment can be used for detecting the optical parameters of a positively-installed LED chip and can also be used for detecting the optical parameters of an inversely-installed LED chip. And simultaneously, the detection accuracy of the optical parameters can be increased.

The invention relates to a preparation method of a semiconductor device and the semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate which comprises a shallow trench and an active region; forming an oxygen-containing layer on the exposed outer surfaces of the shallow trench and the active region; filling a first isolation layer with a set height in the shallow trench of which the surface comprises the oxygen-containing layer, wherein the set height is lower than the height of the active region; forming an etching stop layer on the upper surface of the first isolation layer; filling a second isolation layer on the etching stop layer in the shallow trench to form a shallow trench isolation structure; and etchingthe active region and the shallow trench isolation structure etched to form a word line trench, and the bottom of the word line trench in the shallow trench isolation structure is higher than a set height. According to the preparation method disclosed by the invention, the etching stop layer can be utilized to control the depth of the word line groove in the shallow groove isolation structure, so that the depth of the word line groove is kept consistent with the depth of the word line groove in the active region as much as possible.

The invention discloses a semiconductor device, a semiconductor structure and a manufacturing method of an interconnection structure, belonging to the technical field of semiconductors. The manufacturing method of the interconnection structure comprises the steps that a barrier layer and a seed layer are sequentially formed on a dielectric layer with a groove, and the barrier layer and the seed layer are attached to the dielectric layer in a conformal mode; nitrogen ions are injected into the seed layer according to a preset angle to form a nitrogen-containing seed layer, and the nitrogen-containing seed layer is located on the top surface of the groove and extends towards the bottom of the groove along the two side walls of the groove; the nitrogen-containing seed layer is removed, a metal layer covering the barrier layer is formed, and the groove is filled with the metal layer; and the metal layer and the barrier layer on the top surface of the groove are removed, and planarization processing is performed on the metal layer in the groove to enable the metal layer in the groove to be flush with the surface of the dielectric layer on the top surface of the groove. According to themanufacturing method disclosed by the invention, cavities can be avoided, yield is improved, and meanwhile, the transmission performance of the interconnection structure and the semiconductor device can be improved.

The invention relates to the technical field of semiconductors, particularly to a packaging structure and a packaging method. The packaging structure comprises: a first chip structure; a second chip structure connected to the first chip structure in an inverted mode, wherein the size of the second chip structure is smaller than that of the first chip structure; and a circuit board connected with the first chip structure, wherein the circuit board and the second chip structure are connected to the same surface of the first chip structure, and the circuit board is provided with a connector usedfor being connected with a to-be-connected piece. According to the invention, the second chip structure only occupies a part of the area of the first chip structure, other parts of the first chip structure can be used for being connected with the circuit board, and the first chip structure only occupies a small area of the circuit board, so that the area of the circuit board can be reduced, and the packaging cost can be reduced.