Semiconductor device and producing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, radiation control devices, etc., can solve the problems of high concentration, shallow implantation depth, and increased contact resistance.

Inactive Publication Date: 2004-09-22
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] However, if only the concentration of the source and drain regions is simply reduced, the CoSi formed above 2 The contact resistance between the layers will increase
Therefore, in the invention of Patent Document 1, when the second impurity implantation is performed on the source and drain, the implantation depth is shallower and the concentration is higher.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0086] Using the NMOS transistors in the above-described embodiments, a logic IC product incorporating an SRAM of about 1M bits is configured, and the median value of the leakage current is obtained. Figure 12 Indicates the experimental results.

[0087] As the process conditions for the formation of the source / drain region, the implantation amount of arsenic (As) in the shallow implantation step is changed, and in each implantation amount, the acceleration energy of phosphorus (P) in the deep implantation step and the shallow implantation step are changed. Acceleration energy of arsenic (As), and find out the relationship between the amount of impurity implanted in the shallow implantation step and the median value of the leakage current when the IC is in standby.

[0088] Figure 12 This is a graph showing the relationship between the amount of arsenic (As) implanted and the median value of the leakage current when the IC is in standby based on the results of this experime...

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PUM

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Abstract

To reduce a leakage current by suppressing the generation of a junction leakage. [Means to Solve the Problem]A semiconductor device comprises: a semiconductor region 103, in which an impurity of one conductivity type is doped; a gate insulation layer 105, formed on the semiconductor region 103; a gate electrode 106, formed on the gate insulation layer 105; a lightly doped layer 109a, formed in a region from the principal surface of the semiconductor region 103 to a first depth, in which a first impurity of the other conductivity type is implanted into the semiconductor region 103 with a first dose amount; and a heavily doped layer 109b, formed in a region from the principal surface of the semiconductor region 103 to a second depth, which is shallower than the first depth, in which a second impurity of the other conductivity type is implanted into the semiconductor region 103 with a second dose amount in a range of the first dose amount or more to 1x10E15 / cm<2 >or less.

Description

technical field [0001] The present invention relates to a semiconductor device suitable for a MOS transistor and a manufacturing method thereof. Background technique [0002] Conventionally, as a method of manufacturing a MOS transistor, the following manufacturing method is known. Below, taking N-channel MOS transistors as an example, refer to Figure 13 The structure and manufacturing method thereof will be briefly described. [0003] At a carrier density of 2 x 10 15 / cm 3 On the n-type silicon substrate 301, a carrier density of 3×10 16 / cm 3 P-WELL District 302. Then, boron ions were implanted as channel doping impurities, and a gate oxide film 303 of 20 nm was formed by thermal oxidation. Next, 400nm polysilicon doped with phosphorus is deposited by CVD (Chemical Vapor Deposition) method. Thereafter, the gate region 304 is formed by using a general photolithography process and a dry etching process. Then, Nch adopts the process of implanting phosphorus ions to ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/265H01L21/28H01L21/336H01L27/148
CPCH01L29/7833H01L21/26513H01L29/665H01L29/6659H01L21/2658
Inventor 芳贺泰滨宗佳
Owner SEIKO EPSON CORP
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