Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof
a technology of semiconductor structure and semiconductor wafer, applied in the field of integrated circuits and methods, can solve the problems of insufficient strain in the channel region of forming stressed channel regions, less than optimal,
Active Publication Date: 2018-02-08
GLOBALFOUNDRIES U S INC
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- Abstract
- Description
- Claims
- Application Information
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Benefits of technology
The patent describes a semiconductor structure that includes a piezoelectric layer between two layers of insulating material. This structure can be used in a transistor to create a strain in the channel region, which can modify the charge carrier mobility. The technical effect of this invention is to provide a more efficient and effective semiconductor structure for use in various electronic devices.
Problems solved by technology
Techniques for forming stressed channel regions of field effect transistors as described above can have issues associated therewith.
Some techniques for forming stressed channel regions can yield an insufficient strain in the channel regions when used in semiconductor manufacturing techniques according to advanced technology nodes.
Moreover, strained silicon-on-insulator techniques can provide only one type of strain (tensile or compressive) in each wafer, which may be less than optimal in complementary metal oxide semiconductor (CMOS) techniques wherein both N-channel transistors and P-channel transistors are employed since, as described above, N-channel transistors and P-channel transistors can benefit from different strain.
Method used
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Embodiment Construction
[0020]Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
[0021]The present disclosure will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details whic...
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A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.
Description
BACKGROUND OF THE INVENTION1. Field of the Invention[0001]Generally, the present disclosure relates to integrated circuits, methods for the formation thereof and methods for operating transistors in integrated circuits, and, more particularly, to integrated circuits wherein a strain is provided in channel regions of field effect transistors, methods for the formation of such integrated circuits and methods for operating field effect transistors in such integrated circuits.2. Description of the Related Art[0002]Integrated circuits include a large number of circuit elements, which include, in particular, field effect transistors. In a field effect transistor, a gate structure including a gate electrode and a gate insulation layer may be provided, wherein the gate insulation layer separates the gate electrode from a channel region and provides an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region may ...
Claims
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IPC IPC(8): H01L29/78H01L21/762H01L29/786H01L21/324H01L29/66H01L21/28H01L21/02
CPCH01L29/7849H01L21/28291H01L21/76254H01L29/78654H01L21/02181H01L21/324H01L29/66742H01L21/02356H01L27/1203H01L29/7843H01L29/4908H01L29/66772H01L29/78603H01L29/40111H01L21/76251
Inventor FLACHOWSKY, STEFANILLGEN, RALF
Owner GLOBALFOUNDRIES U S INC
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