10 results about "Charge carrier" patented technology

By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.

Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.

The invention discloses a method for manufacturing a stable high temperature-resistant hydrogen end group conducting channel on a diamond surface. The method comprises the steps of 1, forming a high-resistance diamond layer on a substrate; 2, processing the upper surface of the high-resistance diamond layer to form a hydrogen end group diamond; 3, placing the sample into a gas, solution or collosol containing polar molecules for processing to enable hydrogen end groups in the hydrogen end group diamond to fully adsorb the polar molecules or functional group in the gas, solution or collosol containing polar molecules, thus forming a p type conducting channel at the 10-20nm position of the lower surface of the hydrogen end group diamond and forming a polar molecule adsorbed layer on the upper surface of the hydrogen end group diamond; and 4, taking the sample out to obtain a dielectric barrier layer by depositing at normal temperature. The method can enable the concentration and migration rate of carriers in the p type diamond material channel to be stable in the range of 20-500 DEG C, and further realizing the normal work of a diamond element at high temperature.

The invention relates to a planar coriolis millimeter wave, a terahertz power amplifier and a preparation method thereof, which sequentially comprises a substrate, a channel layer and a coplanar waveguide electrode from bottom to top. The carrier concentration of the channel layer is 1*1014 -1*1017 cm<3>. The length of the channel layer is 1-10 microns. The value range of the product N of the carrier concentration of the channel layer and the length of the channel layer is 1*1011 cm<2> < N < 1*1014 cm <2>. Accoridng to the invention, a coriolis power amplifier with a plane structure is designed, and the device has an obvious negative differential resistance effect. The power amplification from the microwave to the terahertz frequency can be realized. The invetion is beneficial to the application of a planar coriolis device as a microwave or terahertz amplifier in the fields of microwave and terahertz communication, radars, imaging and the like.

The invention discloses a lattice mismatched five-junction solar cell and a preparation method thereof; a GaInP nucleating layer, a GaInAs buffer layer, an AlGaInAs DBR reflecting layer, an AlGaInAs lattice gradient buffer layer, a first GaInAs sub-cell, a second GaInAs sub-cell, a first GaInP sub-cell, a second GaInP sub-cell and a GaInAs cap layer are sequence formed on a Ge substrate; the GaInPnucleating layer, the GaInAs buffer layer and the AlGaInAs DBR reflecting layer are in lattice matching with the Ge substrate; the epitaxial layers of the first GaInAs sub-cell, the second GaInAs sub-cell, the first GaInP sub-cell and the second GaInP sub-cell are in lattice mismatch with the Ge substrate, and lattice matching is kept between the epitaxial layers. According to the solar cell andthe method, the sub-cell carrier collection efficiency and a cell filling factor can be effectively improved, so that the photoelectric conversion efficiency of the five-junction solar cell is improved; compared with most five-junction cells, the structure does not need to grow a GaInNAs epitaxial layer with high quality and harsh growth conditions, and the product development difficulty and the large-scale growth cost are greatly reduced.

The invention discloses a method for measuring organic magnetic resistance of organic semiconductors. The method comprises the steps that first conductance values of the organic semiconductors under the environment without applied magnetic fields are measured; second conductance values of the organic semiconductors under the environment of the applied magnetic fields are measured; and the organicmagnetic resistance is obtained according to the first conductance values and the second conductance values. Through the disclosed method, the magnetic resistance of different organic semiconductor materials can be obtained easily and accurately, then the organic magnetic resistance effects of different organic material devices under different temperatures, electric field intensity, magnetic fields and carrier concentrations can be obtained, and the universal physical method is provided for studying microphysical mechanisms of the different types of organic magnetic resistance devices.

The invention relates to a semiconductor circuit device, comprising a semiconductor substrate (1), a first doped region, a second doped region (2), a connecting doped region (3), and an insulating layer (6) , a conductive structure (4, 5) to be planarized, the charge carriers formed during the planarization step are doped by discharges formed in the first and second doped regions (1, 2) The heterogeneous regions (7) are reliably dissipated and dendrite formation is avoided.