21 results about "Semiconductor structure" patented technology

Buried conductors within semiconductor devices and structures, and methods for forming such conductors, are disclosed. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within the substrate. The conductive elements may be metal, such as tungsten or a tungsten alloy. The invention described in the disclosure provides for advantages including formation of three-dimensional structures without resort to external wiring.

A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

A plasma treatment method for etching a portion of an isolating layer present on a surface of an opening in a semiconductor structure is provided. The method comprising: providing a semiconductor structure comprising an opening in an external surface, wherein the external surface of the semiconductor structure and surfaces defining the opening are at least partially covered by the isolating layer, introducing a treatment gas to the semiconductor structure and the isolating layer, the treatment gas comprising a first component providing forming of a protective polymer during plasma treatment and second component providing etching of the isolating layer during plasma treatment, and treating the semiconductor structure and the isolating layer by inducing a plasma in the treatment gas, such that a protective polymer layer is formed on at least portions of the isolating layer present on the external surface of the semiconductor structure and on at least portions of the isolating layer present on upper portions of sidewalls of the opening, thereby protecting the portions of the isolating layer where the protective polymer layer is being formed, from the plasma, wherein portions of the isolating layer being exposed to the plasma are etched.

A method for fabricating a semiconductor structure includes providing a substrate. The method further includes implanting the substrate to form a high-voltage well region having a first conductivity type. The method further includes forming a pair of drain drift regions in the high-voltage well region. The pair of drain drift regions are on the front side of the substrate, and the pair of drain drift regions have a second conductivity type opposite to the first conductivity type. The method further includes forming a gate electrode embedded in the high-voltage well region. The gate electrode is positioned between the pair of drain drift regions and laterally spaced apart from the pair of drain drift regions.

A method for manufacturing a semiconductor structure comprises the steps that firstly, a semiconductor substrate is provided, a medium layer is formed in the semiconductor substrate, and a hard mask layer is formed in the medium layer and comprises a through hole pattern; secondly, a photoetching bond line comprising a groove pattern is formed in the medium layer; thirdly, the medium layer is etched with the photoetching bond line serving as a mask until the hard mask layer is exposed and a groove is formed, wherein the photoetching bond line comprises the groove pattern; fourthly, the medium layer in which the groove is formed is etched with the hard mask layer and the photoetching bond line serving as the mask until the semiconductor substrate is exposed and a through hole is formed, wherein the photoetching bond line comprises the groove pattern. According to the method for manufacturing the semiconductor structure, the accuracy of the through hole position in the semiconductor structure is improved, and then the stability and the reliability of a device comprising the semiconductor structure are improved.

A semiconductor structure is provided, which includes a first high-voltage MOS device region having a first well and a first light-doping region in a part of the first well, wherein the conductive type of the first well and the conductive type of the first light-doping region are opposite. The first high-voltage MOS device region also includes a first gate stack on a part of the first well and a part of the first light-doping region, and first heavy-doping regions in the first well and the first light-doping region at two sides of the gate stack, wherein the conductive type of the first heavy-doping region and the conductive type of the first well are the same. The first light-doping region between the first well and the first heavy-doping regions is a channel region of the first high-voltage MOS device region.

The invention provides a semiconductor structure and a semiconductor device. In the semiconductor structure and the semiconductor device, a first bonding pad group in a first mixed bonding layer of a first chip and bonding pads in a second bonding pad group in a second mixed bonding layer of a wafer are correspondingly bonded; at least one bonding pad in the at least one second bonding pad group is located in the gap between the two adjacent first chips, and the bonding pads located in the gap are exposed, so that the bonding pads can be directly punctured for electrical testing.

The invention discloses a forming method of a semiconductor structure. The forming method comprises the steps of providing a substrate; forming a core layer on the substrate; ion doping is carried out on the core layer of the sacrificial region, so that the etching rates of the core layer of the sacrificial region and the core layer of the anti-etching region are different, the core layer doped with ions is used as a sacrificial layer, and the core layer not doped with ions is used as an anti-etching layer; forming a groove penetrating through the core layer between the adjacent sacrificial regions; side walls are formed on the side walls of the groove, and the side walls located on the side walls of the groove define a first groove; the sacrificial layer is removed through an etching process, a second groove penetrating through the anti-etching layer is formed, and the etching rate of the etching process on the sacrificial layer is larger than that of the anti-etching layer; and etching the target layer at the bottoms of the first groove and the second groove by taking the anti-etching layer and the side wall as masks to form a target pattern. According to the embodiment of the invention, the pattern precision of the target pattern and the matching degree of the target pattern and the design pattern can be improved.

The invention provides a formation method of a semiconductor structure. The formation method comprises the steps of forming a base, wherein the base comprises a substrate, fin parts and mask layers, wherein the fin parts are arranged on the substrate, and the mask layers are arranged on the fin parts; forming an isolation material layer on the substrate between the fin parts; and forming at least one oxide layer in the fin parts by oxidization step for at least one time, wherein the oxidization step comprises the steps of removing a partial thickness of the isolation material layer so that a part of a side wall of each fin part is exposed out of the isolation material layer; forming a shielding layer on the isolation material layer where the side wall of the fin part is exposed; removing a partial thickness of the isolation material layer below the shielding layer to expose a part of the side wall of the fin part; forming the oxide layer in the fin parts exposed out of the isolation material layer and the shielding layer by oxidization processing; and removing the mask layers and the shielding layer which is used in the oxidization step, wherein the isolation between the fin parts and the substrate can be achieved by the oxidization layer, and the oxidization layer can be used for reducing leakage currents of transistors after the transistors are formed in the fin parts.

The invention provides a forming method of a semiconductor structure, and a semiconductor structure. The forming method of the semiconductor structure comprises: forming a groove in a substrate, the groove dividing the substrate into a first active area and a second active area; forming a first well region in the first active area, forming a second well region in the second active area, and forming a depletion region at the connection position of the first well region and the second well region; performing first ion implantation in the first well region at the bottom of the groove, and performing second ion implantation in the second well region at the bottom of the groove, the type of the first ion implantation being the same as the type of the first well region, the type of the second ion implantation being the same as the type of the second well region; and after the ion implantation, filling a dielectric layer in the groove to form an isolation structure. According to the invention, the method reduces the dimension of the isolation structure and accordingly reduces the occupation area of the isolation structure on a chip; a electrostatic protection circuit can also be quite easily triggered so as to protect a semiconductor device from being damaged; and the latch effect generation probability can also be reduced.

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate, and forming a conductive structure in the substrate; forming a dielectric layer covering the substrate; forming an interconnection opening exposing the conductive structure in the dielectric layer, wherein the interconnection opening comprises a plurality of communicated sub-openings in the thickness direction of the dielectric layer, the interconnection opening at least comprises one opening group, the opening group being composed of two adjacent sub-openings, and in the opening group, the transverse size of the sub-opening far away from one side of the substrate is smaller than that of the other sub-opening; and forming an interconnection structure in the interconnection opening. The manufacturing process for forming the interconnection structure comprises the step of grinding the conductive material in the interconnection opening; and since the transverse size of the sub-opening far away from one side of the substrate is smaller than that of the other sub-opening, in the grinding process, under the action of the opening group, the side wall of the interconnection opening can provide acting force pointing to the side wall of the conductive material, and the probability that the conductive material and the dielectric layer are layered is reduced.

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: forming first core layers on a target layer, wherein the opposite side walls of the adjacent first core layers in a second direction are respectively a first side wall and a second side wall respectively; forming a sacrificial layer covering the first side wall and spaced from the second side wall on the target layer; forming first side walls on the side walls of the first core layer and the sacrificial layer; forming a second core layer between the side wall of the sacrificial layer and the first side wall of the second side wall; forming a filling layer covering the second core layer and the side wall of the first side wall on the target layer; removing the sacrificial layer to form a groove; removing the first side wall located on the side wall of the groove, and forming a second side wall located on the side wall of the groove and a first groove defined by the second side wall; removing the second core layer to form a second groove; removing the first core layer to form a third groove; and patterning the target layer below the first groove, the second groove and the third groove to form a target pattern. The embodiment of the invention is beneficial to improving the pattern precision of the target pattern.

The invention discloses a semiconductor device, a semiconductor structure and a manufacturing method of an interconnection structure, belonging to the technical field of semiconductors. The manufacturing method of the interconnection structure comprises the steps that a barrier layer and a seed layer are sequentially formed on a dielectric layer with a groove, and the barrier layer and the seed layer are attached to the dielectric layer in a conformal mode; nitrogen ions are injected into the seed layer according to a preset angle to form a nitrogen-containing seed layer, and the nitrogen-containing seed layer is located on the top surface of the groove and extends towards the bottom of the groove along the two side walls of the groove; the nitrogen-containing seed layer is removed, a metal layer covering the barrier layer is formed, and the groove is filled with the metal layer; and the metal layer and the barrier layer on the top surface of the groove are removed, and planarization processing is performed on the metal layer in the groove to enable the metal layer in the groove to be flush with the surface of the dielectric layer on the top surface of the groove. According to themanufacturing method disclosed by the invention, cavities can be avoided, yield is improved, and meanwhile, the transmission performance of the interconnection structure and the semiconductor device can be improved.

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: forming a base, wherein the base comprises a substrate, a grid material layer located on the surface of the substrate, a dielectric layer covering the surface of the grid material layer, and a barrier layer covering the surface of the dielectric layer; forming and only forming a mask layer on the surface of the barrier layer, wherein the etching selection ratio between the mask layer and the barrier layer is greater than a preset value; patterning the mask layer; and transferring the pattern in the mask layer to the grid material layer to form a grid. The using amount of mask layer materials and the number of machines used for depositing the mask layers are reduced; and moreover, the etching step for forming the grid is reduced, so that the use amount of an etching agent is reduced, the etching time is shortened, the production efficiency of a semiconductor structure is correspondingly improved, and the production cost is reduced.

The invention discloses a pattern correction method and a semiconductor structure forming method, and the pattern correction method comprises the steps: providing a to-be-corrected layout which is provided with a plurality of first to-be-corrected patterns, the first to-be-corrected patterns being provided with first points, and the adjacent first to-be-corrected patterns being connected through the first points; obtaining a first line segment and a second line segment of a first to-be-corrected graph, wherein the first line segment is connected with the first point; correcting a second type of line segments of the first to-be-corrected graph to obtain a corrected layout which comprises a first corrected graph; and performing optical proximity effect correction on the correction layout. The first correction pattern obtained by the method is subjected to optical proximity effect correction to obtain a photoetched pattern, and the size precision of the photoetched pattern is relatively high.

The invention discloses a semiconductor structure and a manufacturing method thereof. The method comprises the following steps: forming an electric connecting piece on a circuit substrate, defining a preset position of a via hole on a printing layer on a rewiring layer in a transfer printing manner, reconfiguring an electric connecting layer on the preset position, and jointing the circuit substrate comprising the electric connecting piece with the rewiring layer comprising the electric connecting layer, wherein the electric connection layer is electrically connected with the electric connection piece through reflow soldering. The electrical connection between the rewiring layer and the circuit substrate is realized by accurately defining the electrical contact between the rewiring layer and the circuit substrate.

The invention provides a semiconductor structure and a preparation method thereof, a three-dimensional memory, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims to improve the stability of the three-dimensional memory. The preparation method comprises the following steps: forming an initial laminated structure on one side of a substrate, wherein the initial laminated structure comprises gate replacement layers and initial gate dielectric layers which are alternately laminated; forming a channel hole; an initial channel structure is formed in the channel hole, the initial channel structure comprises a barrier layer and an initial charge storage layer which are arranged in sequence, and the barrier layer and the initial gate dielectric layer are different in etching rate under the same process condition; removing the initial gate dielectric layer to form a first gap; performing insulation processing on a target part of the initial charge storage layer through the first gap so as to convert the target part into an isolation part; and the first gap is filled with an insulating material. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.