7 results about "Etching rate" patented technology

An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; and, a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line; wherein an etching rate of the separating layer approaches that of the substrate.

A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

The invention provides a flexible semiconductor composite film and a preparation method thereof. The flexible semiconductor composite film is prepared by providing a heterocomposite structure comprising a sacrificial substrate and a heterocomposite film on the surface of the sacrificial substrate. The sacrificial substrate has an etching surface, and a groove structure extending inwardly from theetching surface is formed in the sacrificial substrate. The heterocomposite film is located on the surface of the etching surface. Providing a flexible substrate bonding the flexible substrate to a side of the heterogeneous film remote from the etching surface; Flexible semiconductor composite films are prepared by etching sacrificial substrate and heterogeneous film. The flexible semiconductor composite film of the invention and the preparation thereof increase the etching rate of the later stage and also ensure the integrity of the prepared flexible semiconductor film by photoetching the groove structure in a sacrificial substrate (such as an oxide layer); Heterocomposite structure prepare by ion implantation and stripping is combine with chemical etching, so that that preparation of theflexible single crystal semiconductor film can cover most of the semiconductors.

The invention discloses an etching solution suitable for dislocation display of a crystal orientation [100] monocrystal germanium wafer deflecting to the crystal orientation [111] as well as an etching method. The method comprises steps as follows: preparing the etching solution; placing the prepared etching solution in a thermostat water bath for heating; cleaning the surface of the monocrystal germanium wafer; soaking the monocrystal germanium wafer in the etching solution for etching for 5 min; performing leaching and blow-drying on the etched monocrystal germanium wafer; observing the morphology after etching under a metallographic microscope finally. With the adoption of the etching method, a dislocation pit can be effectively etched out, the etching rate is moderate, the reaction process is mild and controllable, the etching method is simple and feasible when used for detecting the dislocation density of the crystal orientation [100] monocrystal germanium wafer deflecting to the crystal orientation [111], and the appearing probability of interference patterns such as water ripples and the like is low.

The invention discloses a forming method of a semiconductor structure. The forming method comprises the steps of providing a substrate; forming a core layer on the substrate; ion doping is carried out on the core layer of the sacrificial region, so that the etching rates of the core layer of the sacrificial region and the core layer of the anti-etching region are different, the core layer doped with ions is used as a sacrificial layer, and the core layer not doped with ions is used as an anti-etching layer; forming a groove penetrating through the core layer between the adjacent sacrificial regions; side walls are formed on the side walls of the groove, and the side walls located on the side walls of the groove define a first groove; the sacrificial layer is removed through an etching process, a second groove penetrating through the anti-etching layer is formed, and the etching rate of the etching process on the sacrificial layer is larger than that of the anti-etching layer; and etching the target layer at the bottoms of the first groove and the second groove by taking the anti-etching layer and the side wall as masks to form a target pattern. According to the embodiment of the invention, the pattern precision of the target pattern and the matching degree of the target pattern and the design pattern can be improved.

The invention provides a semiconductor structure and a preparation method thereof, a three-dimensional memory, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims to improve the stability of the three-dimensional memory. The preparation method comprises the following steps: forming an initial laminated structure on one side of a substrate, wherein the initial laminated structure comprises gate replacement layers and initial gate dielectric layers which are alternately laminated; forming a channel hole; an initial channel structure is formed in the channel hole, the initial channel structure comprises a barrier layer and an initial charge storage layer which are arranged in sequence, and the barrier layer and the initial gate dielectric layer are different in etching rate under the same process condition; removing the initial gate dielectric layer to form a first gap; performing insulation processing on a target part of the initial charge storage layer through the first gap so as to convert the target part into an isolation part; and the first gap is filled with an insulating material. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.