11 results about "Contact hole" patented technology

A method for forming a mask for forming contact holes of a semiconductor device includes coating an etch target layer with a first photoresist layer, patterning the first photoresist layer in a type of lines and spaces to form a first photoresist pattern, wherein the first photoresist pattern comprises pads formed at both ends of the first photoresist pattern, and lines repeatedly formed between the pads at the both ends, forming a protective layer on a surface of the first photoresist pattern by performing a freezing process onto the first photoresist pattern, and forming a second photoresist pattern having a type of lines stretched in a second direction which is perpendicular to the first direction on the etch target layer including the protective layer.

A manufacture method for a trumpet-shaped contact includes the following steps of: forming a first insulating layer on a silicon underlay which is formed with an active structure, an isolation and a metal silicide; then forming a second insulating layer; forming a photosensitive resist and forming a contact hole pattern of the photosensitive resist by photoetching and developing; etching the second insulating layer and the first insulating layer to form a contact hole; returning the photosensitive resist; carrying out the etching adopting a gas with high selectivity ratio of the second insulating layer/the first insulating layer on the second insulating layer and the first insulating layer to form a trumpet-shaped contact hole; removing the photosensitive resist; filling and contacting metals as well as flatting; forming a dielectric medium layer between metals and etching a metal wire pattern; filling a first metal and flatting; continuing other manufacture processes. The trumpet-shaped contact manufactured by the method can prevent the dispersing of copper.

A liquid crystal display includes: a substrate; a display region on the substrate, the display region comprising: one or more gate lines overlying the substrate; a gate insulating layer overlying the gate lines; a semiconductor layer overlying the gate insulating layer; one or more pairs of source and drain electrodes overlying the semiconductor layer, each pair being a pair of one source electrode and one corresponding drain electrode facing the source electrode; one or more data lines overlying the semiconductor layer, each data line comprising one or more of the source electrodes, wherein a display area is provided at each intersection of the data lines with the gate lines; a passivation layer overlying the data lines and the drain electrodes and comprising a plurality of contact holes; and one or more color filters overlying the passivation layer and comprising a plurality of through holes. In top view, the semiconductor layer has the same shape as the data lines and the drain electrodes except over each region between each source electrode and the corresponding drain electrode. The contact holes' edges are aligned with the through holes' edges.

The present invention provides an OLED display substrate and a manufacture method thereof. The OLED display substrate comprises a substrate (10), a TFT (90) located on the substrate (10), a passivation layer (50) located on the TFT (90), a flat layer (60) located on the passivation layer (50), a connecting electrode (80) being located on the flat layer (60) and contacting the TFT (90), an anode (70) being located on the flat layer (60) and covering the connecting electrode (80), an organic emitting layer (71) located on the anode (70) and a cathode (72) located on the organic emitting layer (71); the connecting electrode (80) contacts the TFT (90) via the contact hole (81) penetrating the flat layer (60) and the passivation layer (50); the anode (70) is electrically connected to the TFT (90) via the connecting electrode (80); the short circuit between the cathode and anode of the OLED display substrate can be prevented for avoiding the current concentration and ensuring the normal illumination of the OLED.

The invention relates to an antitheft backpack with multiple conductive materials being embedded into zipper teeth. The antitheft backpack comprises a backpack body with an opening, a conductive zipper, an alarm module and a power supply module, wherein the conductive zipper comprises zipper chains, the zipper teeth and two zipper pullers; first sides, opposite to other zipper teeth, of the front ends of the zipper teeth are provided with contact protrusions, and contact holes are formed in second sides opposite to the first sides; the zipper teeth are made of insulating materials, the multiple conductive materials which are not connected are embedded into the front ends of the zipper teeth to form conductive parts which are exposed from the contact protrusions and the contact holes, the two zipper pullers are oppositely arranged on the zipper chains, and the zipper teeth are meshed under the action of the zipper pullers to form a conductive wire. The antitheft backpack has the advantages that a traditional zipper is changed into the conductive zipper and turned into a sensor at the same time; when the zipper pullers are separated, the conductive zipper is disconnected, an alarm gives out an alarm, other people are prevented from privately opening the backpack without the consent of a user, and an antitheft effect is achieved.

The invention relates to a connection structure of a door hinge fixing plate, which comprises an upper splint and a lower splint fixedly connected to each other, a fixed interlayer is arranged between the upper splint and the lower splint, and two clamping plates are mirror-symmetrically arranged in the fixed interlayer , the clamping plate is arc-shaped, one end of the clamping plate is clamped in the fixed interlayer, an opening is arranged in the middle of the lower clamping plate, and the other end of the clamping plate extends to the outside of the fixed interlayer through the opening; There is an expansion screw threaded in the middle of the upper splint, and an expansion column is arranged between the clamping plates. The expansion column is cylindrical, and its side wall is in contact with the inner side wall of the clamping plate. The surface is set in several conical positioning holes, the axis of the positioning holes is located on the radial axis of the expansion column, and the end of the expansion screw is tapered, contacting the positioning holes of the expansion block.

The embodiment of the invention discloses a manufacturing method for a low-temperature polycrystalline silicon thin film transistor and an array substrate and relates to the technical field of display. The manufacturing method solves the technical problem that a source electrode or a drain electrode does not make good contact with an active layer. The manufacturing method comprises the steps that a pattern containing the active layer is formed on a substrate, wherein the active layer contains low-temperature polycrystalline silicon; a gate insulation layer is formed on the substrate where the pattern containing the active layer is formed; a pattern containing a grid electrode is formed on the substrate where the gate insulation layer is formed; an interlayer insulating layer is formed on the substrate where the pattern containing the grid electrode is formed, and contact holes corresponding to the source electrode and the drain electrode are formed in the interlayer insulating layer and the gate insulation layer through a composition process; the low-temperature polycrystalline silicon is formed at the bottoms of the contact holes; a pattern containing the source electrode and the drain electrode is formed, and the source electrode and the drain electrode are connected with the active layer through the contact holes and the low-temperature polycrystalline silicon at the bottoms of the contact holes.

The invention discloses a method of manufacturing a semiconductor device. The method comprises the following steps: a semiconductor substrate is provided; a virtual gate electrode is formed on the semiconductor substrate; a sacrificial material layer is formed on the semiconductor substrate and the virtual gate electrode; planarization technology is executed to enable the top part of the virtual gate electrode to be exposed; the virtual gate electrode is etched and removed to form a groove, and a metal gate electrode is formed in the groove; and the sacrificial material layer is removed. According to the manufacturing technology of the invention, the problems that etching of a contact hole stops and connection of the contact hole is short-circuited when the contact hole in the semiconductor device with the high K dielectric/metal gate electrode is manufactured can be effectively avoided.

A bonding pad layer system is deposited on a semiconductor chip as a base, for example, a micromechanical semiconductor chip, in which at least one self-supporting dielectric membrane made up of dielectric layers, a platinum conductor track and a heater made of platinum is integrated. In the process, the deposition of a tantalum layer takes place first, upon that the deposition of a first platinum layer, upon that the deposition of a tantalum nitride layer, upon that the deposition of a second platinum layer and upon that the deposition of a gold layer, at least one bonding pad for connecting with a bonding wire being formed in the gold layer. The bonding pad is situated in the area of the contact hole on the semiconductor chip, in which a platinum conductor track leading to the heater is connected using a ring contact and/or is connected outside this area.