Atomic-scale precision lossless layer-by-layer etching method for two-dimensional layered material

一种二维层状、原子级的技术,应用在电气元件、半导体/固态器件制造、电路等方向,能够解决保留层晶格损伤、差刻蚀选择性、电学性能下降等问题

Active Publication Date: 2021-09-21
NANJING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] So far, all the reported two-dimensional material etching technologies for CMOS applications have an obvious disadvantage, that is, they have poor etching selectivity; during the etching process, high-energy etching media will act on the material to be prepared Etching layer and reserved layer, thus causing lattice damage and significant degradation of electrical properties of the reserved layer

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] This example introduces a non-destructive layer-by-layer etching method with atomic-level precision for two-dimensional layered materials.

[0048] The difficulty of the present invention is to realize the following two points simultaneously in material etching processing:

[0049] 1) Obtain high-precision etching at the single-atom level;

[0050] 2) Obtain an ultra-high etching selectivity ratio, so that the etching medium can effectively remove the etching layer without damaging the material retention layer and maintain its intrinsic physical properties.

[0051] Please refer to figure 1 , figure 1 A flow chart of an atomic-level precision non-destructive layer-by-layer etching method for a two-dimensional layered material provided by the present invention, which shows a two-dimensional layered material atomic-level precision non-destructive layer-by-layer etching method, including the following steps :

[0052] Please refer to figure 2 , figure 2 A schematic...

Embodiment 2

[0068] Based on the above-mentioned embodiment 1, this embodiment introduces in detail a non-destructive layer-by-layer etching method with atomic-level precision for a two-dimensional layered material.

[0069] Step 1: Use the mechanical stripping method to remove the MoS to be etched 2 The nanosheets are transferred to silicon wafers.

[0070] Step 2: Spin-coat PMMA electron beam glue, and define the area to be etched by electron beam exposure.

[0071] Step 3: Pattern the MoS to be etched 2 The nanosheets were placed in reactive ion etching (RIE), and were bombarded with plasma for 30s at low power (30W) to introduce lattice defects on the surface of the area to be etched.

[0072] Step 4: On the MoS to be etched 2 10nm metallic aluminum was vapor-deposited on the nanosheet as a thermal diffusion sacrificial layer.

[0073] Step 5: Using a solvent stripping method to remove the PMMA glue and the upper layer of aluminum, leaving only the aluminum sacrificial layer on the...

Embodiment 3

[0079] Based on the above-mentioned embodiment 2, this embodiment mainly introduces a nondestructive layer-by-layer etching method with atomic-level precision for a two-dimensional layered material.

[0080] Step 1: Use the mechanical stripping method to remove the MoS to be etched 2 The nanosheets are transferred to silicon wafers.

[0081] Step 2: Repeat steps 2-7 in Example 2 to etch the monolayer along the vertical direction to form strip-shaped thinning regions with vertical periodic structures.

[0082] Step 3: Repeat steps 2-7 in Example 2 to etch the single layer along the horizontal direction to form strip-shaped thinning regions with a horizontal periodic structure.

[0083] Please refer to Figure 8 , Figure 8 In the atomic-level precision non-destructive layer-by-layer etching method of a two-dimensional layered material provided by the present invention, MoS is etched twice along the vertical and horizontal directions. 2 A surface-defined checkerboard pattern...

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PUM

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Abstract

The invention provides an atomic-scale precision lossless layer-by-layer etching method for a two-dimensional layered material. The method comprises the following steps of: manufacturing lattice defects on the surface layer of a material to be etched by using a surface treatment technology; depositing a thermal diffusion sacrificial material on the surface layer of the material to be etched; performing thermal annealing on the material to be etched at a certain temperature, so that the diffusion sacrificial material is diffused into the surface layer of the material to be etched to form an alloy layer; and removing the diffusion sacrificial material and the alloy layer thereof by using a selective chemical reaction to finish local etching, wherein the two-dimensional layered material to be etched comprises one or a combination of metal sulfide, metal selenide, metal telluride, graphene and black phosphorus, and the diffusion sacrificial material comprises one or combination of low-atomic-radius metal, low-atomic-radius non-metal material and small-molecular organic matter. The sacrificial layer does not diffuse into an internal retention layer of the material to be etched, so that the etching process does not damage crystal lattices of the material retention layer, the intrinsic electrical property of the material is maintained, and the atomic-scale precision lossless layer-by-layer etching method is a lossless etching technology.

Description

technical field [0001] The invention relates to the field of semiconductor material processing, in particular to an atomic-level precision non-destructive layer-by-layer etching method for two-dimensional layered materials. Background technique [0002] As the size of semiconductor microelectronic transistors continues to shrink, Moore's Law is gradually approaching the physical limit of material processing. The degradation of channel mobility due to factors such as etching precision and thickness fluctuation is the main bottleneck limiting the further shrinkage of silicon-based devices. The way to break through this bottleneck is to develop a semiconductor channel with atomic-level thickness and flatness and its matching etching processing technology. Two-dimensional materials with a layered atomic structure meet the structural requirements of the above materials, and are strong candidates for next-generation semiconductor channel materials, and have received extensive att...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/3213
CPCH01L21/32133H01L21/32139Y02P70/50
Inventor 黎松林周健
Owner NANJING UNIV
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