9 results about "Hard mask" patented technology

Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of first hard mask layer using a chlorine-based plasma or a sulfur fluoride-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma, wherein a portion of the layer of copper containing conductive metal residing below a portion of the first hard mask layer that remains after the second sputter etch forms the one or more conductive lines. In one embodiment, the second plasma is a fluorocarbon-based plasma.

A method of forming an etch mask includes: providing a substrate having thereon a material layer to be etched; forming a hard mask layer consisting of a radiation-sensitive, single-layer resist material on the material layer; exposing the hard mask layer to actinic energy to change solvent solubility of exposed regions of the hard mask layer; and subjecting the hard mask layer to water treatment to remove the exposed regions of the hard mask layer, thereby forming a masking pattern consisting of unexposed regions of the hard mask layer.

In an etching method for achieving a dual damascene structure by using at least one layer of a low-k film and at least one layer of a hard mask, a dummy film, which is ultimately not left in the dual damascene structure, is formed in at least one layer over the hard mask in order to prevent shoulder sag. By adopting this method, a dual damascene structure in which the extent of the shoulder sag at the hard mask is minimized can be achieved through etching.

A process for forming a void-free dielectric layer is disclosed in which adjoining gate film stacks are formed on a semiconductor substrate. Each gate film stack includes a silicide layer and a hard mask that overlies the silicide layer. A first selective etch is performed so as to reduce the width of the hard mask on each of the gate film stacks, exposing portions of the top surface of the silicide layer. A second selective etch is then performed to reduce the width of the silicide layer. Spacers are then formed on opposite sides of each of the gate film stacks, and a dielectric film is formed that extends over the gate film stacks. By reducing the width of the hard mask layer and the silicide layer, gate film stacks are obtained that have reduced width near the top of each gate film stack, preventing voids from forming in the dielectric film.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

A method for manufacturing a semiconductor structure comprises the steps that firstly, a semiconductor substrate is provided, a medium layer is formed in the semiconductor substrate, and a hard mask layer is formed in the medium layer and comprises a through hole pattern; secondly, a photoetching bond line comprising a groove pattern is formed in the medium layer; thirdly, the medium layer is etched with the photoetching bond line serving as a mask until the hard mask layer is exposed and a groove is formed, wherein the photoetching bond line comprises the groove pattern; fourthly, the medium layer in which the groove is formed is etched with the hard mask layer and the photoetching bond line serving as the mask until the semiconductor substrate is exposed and a through hole is formed, wherein the photoetching bond line comprises the groove pattern. According to the method for manufacturing the semiconductor structure, the accuracy of the through hole position in the semiconductor structure is improved, and then the stability and the reliability of a device comprising the semiconductor structure are improved.

The invention provides a method for rounding the top of a trench. The method comprises the following steps of: forming a hard mask layer on a substrate and defining a trench region pattern by using aphotoetching process; etching the hard mask layer according to the trench region pattern, wherein the upper surface of the substrate is an etching stop layer; carrying out wet etching on the substratealong the side wall of the hard mask layer to form the shallow region trench of the substrate; continuously etching the substrate along the side wall of the hard mask layer by adopting a dry etchingprocess to form a deep region trench communicating with the shallow region trench of the substrate; removing the hard mask layer, and performing a filleting process on the top of the trench; and performing sacrificial oxidation on the trench, and further rounding the top of the trench. According to the method, after the hard mask layer is opened, one-step wet etching is firstly carried out, then trench etching is carried out, the hard mask layer is removed through wet etching after trench etching, then filleting is carried out on the trench through a filleting process, the effect of filletingthe top of the trench can be achieved, the process is simplified, and the production cost is reduced.