15 results about "Semiconductor components" patented technology

A method for growing a crystal of an Al-containing III-V group compound semiconductor by the conventional HVPE method, characterized in that it comprises a step of reacting Al with hydrogen halide at a temperature of 700° C. or lower to form a halide of Al. The method has allowed the suppression of the formation of aluminum chloride (AlCl) or aluminum bromide (AlBr) reacting violently with quartz, which is the material of a reaction vessel for the growth, resulting in the achievement of the vapor phase growth of an Al-containing III-V group compound semiconductor at a rate of 100 microns/hr or more, which has lead to the mass-production of a substrate and a semiconductor element having satisfactory resistance to adverse environment.

A semiconductor carrier film includes (i) a base film having insulating property, (ii) a barrier layer provided on the base film, the barrier layer including nickel-chrome alloy as a main component, and (iii) a wire layer provided on the barrier layer, the wire layer being made of conductive material including copper, and a ratio of chrome in the barrier layer is 15% to 50% by weight. A semiconductor device is formed by bonding a semiconductor element to the wire layer. The semiconductor carrier film and the semiconductor device are suitable for attaining finer pitches and higher outputs, because insulating resistance between adjacent terminals is less likely to deteriorate then in conventional art even in the environment of high temperature and moisture.

Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.

A semiconductor device includes a metal member, a semiconductor element, a resin part, a primer layer, and a peel-off restraining part. The metal member has a surface that includes a semiconductor element mounting region and a resin close contact region that extends from the semiconductor element mounting region to an outer peripheral edge of the metal member. The semiconductor element is mounted on the semiconductor element mounting region. The resin part extends to a position outside a side surface of the metal member, and closely contacts with the resin close contact region, and collectively covers the semiconductor element and the metal member. The primer layer is disposed between the resin close contact region and the resin part. The peel-off restraining part is configured to restrain the metal member and the resin part from peeling from each other in the outer peripheral part of the resin close contact region.

An object of the present invention is to provide a thermosetting die-bonding film that is capable of preventing warping of an adherend by suppressing curing contraction of the film after die bonding, and a dicing die-bonding film. The present invention relates to a thermosetting die-bonding film for adhering and fixing a semiconductor element onto an adherend, comprising at least an epoxy resin and a phenol resin as a thermosetting component, wherein the ratio of the number of moles of epoxy groups to the number of moles of phenolic hydroxyl groups in the thermosetting component is in a range of 1.5 to 6.

The invention provides a semiconductor element, a packaging structure and a forming method of a semiconductor element. A solder bump provided in the semiconductor element is disposed on a welding pad and is electrically connected to the welding pad. A metal cover layer is disposed at a part of the welding bump. The melting point of the metal cover layer is higher than that of the welding bump. The invention is advantageous in that the metal cover layer can be used as a hardstop element; the bump structure after packaging can maintain a consistent height; the problem of short circuit or bridgejoint can be reduced and even prevented.

A semiconductor component forming method includes providing a semiconductor substrate with the surface provided with a gate electrode structure; forming a mask layer covering the semiconductor substrate and the gate electrode structure; forming a photoresist protection layer on the surface of the mask layer by the deposition process; forming a graphical photoresist layer on the surface of the photoresist protection layer; adopting the graphical photoresist layer as a mask, etching the photoresist protection layer and the mask layer, and forming a graphical photoresist protection layer and a graphical mask layer; adopting the graphical photoresist protection layer and the graphical mask layer as masks, etching a certain thickness of the semiconductor substrate adjacent to the gate electrode structure, and forming grooves; removing the graphical photoresist layer; removing the graphical photoresist protection layer; forming stress layers fulfilling the grooves by epitaxy technique. The selectivity of the epitaxy technique is improved, the growth of stress layer material on an unexpected region is avoided, and the electrical properties of the semiconductor component are improved.

The invention provides a semiconductor element and a manufacturing method thereof. The manufacturing method comprises: a substrate having a plurality of stacking structures is provided, the spaces among the stacking structures are coated with fluid materials, and the parts of fluid materials are removed to form a sacrificial layer exposing the parts of stacking structures; a plurality of dielectric clearance walls are formed at the side walls of the exposed stacking structures and the sacrificial layer is removed completely; and a dielectric layer covering the stacking structures is formed on the substrate and an air clearance is formed between the two stacking structures below the dielectric clearance walls. According to the invention, a depth-width ratio of a groove is reduced and thus clearance is filled; and the air clearance for avoiding a coupling effect between gates is also formed.

A semiconductor module which includes a plurality of control circuits that respectively drive a plurality of semiconductor elements on and off and a plurality of signal output circuits for the respective control circuits and which output operation status information, where the signal output circuits are respectively provided with signal output terminals having an open-drain configuration, and the signal output terminals each are connected to an internal lead frame on which the power semiconductor elements and the control circuits are mounted.

The invention relates to a method for preparing cubic boron nitride (cBN) single crystal-film homogeneous P-N junction, and belongs to a method for preparing semiconductor components. The method comprises the steps of: synthesizing a semiconducting cBN single crystal with semiconductor characteristic and preparing a doped cBN film, wherein the cBN film has the semiconductor characteristic opposite to that of the cBN single crystal; the semiconducting cBN single crystal with the semiconductor characteristic is synthesized by a high-pressure direct synthesis method or a high-pressure re-diffusion method; and the doped cBN film is prepared by taking the semiconducting cBN single crystal with the semiconductor characteristic as a substrate and doping and growing a cBN film with a semiconductor type opposite to a substrate type by a vacuum vapor deposition method. The vacuum vapor deposition method is a vacuum physical vapor deposition method or a vacuum chemical vapor deposition method. The method has the advantages of reduction in processing difficulties, improvement on production efficiency, yield and the like and great improvement compared with the conventional technology for preparing a cBN homogeneous P-N junction by high-pressure systemization and re-growth processes.

A semiconductor device of the present invention includes a supporting board, an electrode surface processing layer formed on the supporting board, a semiconductor element, and a solder material containing a first metal composed mainly of bismuth and a second metal having a higher melting point than the first metal and joining the electrode surface processing layer and the semiconductor element, the first metal containing particles of the second metal inside the first metal. The composition ratio of the second metal is higher than the first metal in a region of the solder material corresponding to the center portion of the semiconductor element, and the composition ratio of the second metal is at least 83.8 atomic percent in the region corresponding to the center portion.

A semiconductor device includes a plurality of electrode pads P provided on a semiconductor element 1, leads L coupled with the electrode pads via bonding wires W and common lines 2a and 2b provided on the semiconductor element 1 that achieve electrical continuity for electrode pads that handle a common signal among the plurality of electrode pads. At least the surfaces of the common lines 2a and 2b are covered with an insulating member, i.e., a second insulating adhesive tape. With this, the loops of the bonding wires can be lowered, thereby achieving a thinner package.