15 results about "Ion implantation" patented technology

A supported graphene device comprises at least one graphene feature of 1 to about 10 graphene layers having a predetermined shape and pattern, with at least a portion of each graphene feature being supported on a substrate. In some embodiments the device comprises graphene features supported on crystalline semiconductor substrate, such as silicon or germanium. The graphene features on a crystalline semiconductor substrate can be fabricated by forming an amorphous carbon doped semiconductor on the crystalline semiconductor substrate and then epitaxially crystallizing the amorphous semiconductor with carbon migration to the surface to form a graphene feature of one or more graphene layers. The epitaxy can be promoted by heating the device or by irradiation with a laser. Methods for fabricating graphene on a variety of substrates, over large areas with controlled thicknesses employ ion implantation or other doping techniques followed by pulsed laser annealing or other annealing techniques that result in solid phase regrowth are presented.

The invention provides an aluminum and aluminum alloy matrix aluminum nitride reinforced gradient composite surface layer. In the surface layer, aluminum and an aluminum alloy matrix are melted by nitrogen arc with a simple process to ensure that Al and N elements in a melting bath to perform nitridation reaction, namely Al reacts with N to generate AlN, so as to obtain the 'AlN reinforced gradient composite surface layer'. Compared with a thin surface nitridated (AlN) layer prepared by reactive sputtering, chemical vapor deposition, ion injection, plasma nitridation and other methods, the surface layer has large thickness (0.13-0.3mm), has the microstructural characteristic of surface gradient composites, and has remarkably improved microhardness and abrasion resistance compared with the aluminum and the aluminum alloy matrix.

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with a transverse composite buffer layer structure, belonging to the technical field of power semiconductors. In the invention, the transverse composite buffer layer structure is introduced into an electric conducting channel region in a drift region of a conventional LDMOS device; the transverse composite buffer layer structure consists of an N-type doped pillar region and a P-type doped pillar region which are transversely arrayed at intervals; and the N-type doped pillar region and the P-type doped pillar region are parallel to the current direction between a source electrode and a drain electrode of the whole device. In the invention, the transverse composite buffer layer structure is adopted to ensure that the pressure-resistant performance of the device can be improved and the specific on-resistance of the device is reduced; when the device is manufactured, a plurality of high-energy ion implantations and knot pushing are adopted to respectively form the N-type doped pillar region and the P-type doped pillar region; the composite buffer layer is of a transverse structure; and therefore, the N-type doped pillar region and the P-type doped pillar region with better process consistency can be obtained, the problem that the concentration of a conducting layer among multilayer doped buried layers in a longitudinal composite buffer layer structure is reduced is not caused and the LDMOS device with more excellent performances is obtained.

A resist removing device 1 functions to remove a resist from a substrate while preventing occurrence of popping phenomenon and at the same time attains reduction in cost of energy for the resist removing and has a simplified constitution. The resist removing device 1 is equipped with a chamber 2 for containing therein a substrate 16 (for example, a substrate having a high-doze ion implanted resist), and with a pressure below the atmospheric pressure, the chamber 2 is fed with ozone gas, unsaturated hydrocarbons and water vapor. The ozone gas may be an ultra-high concentrated ozone gas that is produced by subjecting an ozone containing gas to a liquefaction-separation with the aid of a vapor pressure difference and then vaporizing the liquefied ozone. For cleaning the substrate 16 thus treated, it is preferable to use ultra-pure water. The chamber 2 is equipped with a susceptor 15 for holding the substrate 16. The susceptor 15 is heated to a temperature of 100° C. or below. An example of the means of heating the susceptor is a light source that emits infra-red rays.

The invention provides an ion implantation device. The device comprises a shielding room, an ion source, an extraction electrode, an analyzer, an analysis diaphragm, a focusing lens, an accelerating tube, a symmetric electrostatic scanning electrode and a uniform magnetic field parallel lens which are successively arranged. A first chamber and a second chamber which are isolated from each other are arranged in the shielding room. A high-voltage bin is arranged in the first chamber. A target chamber is arranged in the second chamber. The ion source, the extraction electrode, the analyzer and the analysis diaphragm are arranged in the high-voltage bin. The accelerating tube is arranged in the first chamber. A first outlet for an ion beam to enter the accelerating tube is formed in the high-voltage bin. The first chamber is provided with a second outlet for the ion beam to enter the symmetric electrostatic scanning electrode. The symmetric electrostatic scanning electrode and the uniformmagnetic field parallel lens are arranged in the second chamber. A target table, an orientation table, a wafer library and at least one manipulator for transferring wafers are arranged in the target chamber. The target chamber is provided with an injection port for the ion beam to be injected into the wafers on the target table. The device provided by the invention has the advantages of simple structure, low cost, convenience for realizing high-energy high-precision injection and the like.

A change of a beam current of an ion beam which passes an outside of the side of a forestage beam restricting shutter, and which is incident on a forestage multipoints Faraday is measured while the forestage beam restricting shutter is driven in a y direction by a forestage shutter driving apparatus in order to obtain a beam current density distribution in the y direction of the ion beam at a position of the forestage beam restricting shutter. A change of a beam current of the ion beam which passes an outside of the side of a poststage beam restricting shutter, and which is incident on a poststage multipoints Faraday is measured while the poststage beam restricting shutter is driven in the y direction by a poststage shutter driving apparatus in order to obtain a beam current density distribution in the y direction of the ion beam at a position of the poststage beam restricting shutter. By using these results, an angle deviation, a diverging angle, and/or a beam size in the y direction of the ion beam can be obtained.

The invention provides a magnetic disk that solves (1) a problem of cross-talk that cannot be solved even by an existing thermally assisted recording method or a discrete method (DTM or the like), (2) a problem of surface flatness, which an existing embedding type DTM or the like has, and (3) a problem of a difference in thermal expansion coefficient between materials when a thermally assisted method is applied to the DTM, and that (4) does not necessitate a special medium structure, and is excellent in a surface flatness and economically and functionally high in realizability. A DTM manufactured by ion implantation is excellent in the surface flatness, and can solve the cross-talk problem by conducting the thermally assisted recording at a temperature between a Curie temperature (Tcn) of a portion where ions are implanted (non-recording region) and a Curie temperature (Tcr) of a portion where ions are not implanted (recording region).

The invention relates to a solid-state plasma PiN diode and a preparation method therefor. The preparation method comprises the steps of selecting an SOI substrate; etching the SOI substrate to form an isolation groove; filling the isolation groove to form an isolation region, wherein the depth of the isolation groove is greater than or equal to the thickness of top layer silicon of the SOI substrate; etching the SOI substrate to form a P type trench and an N type trench; performing ion implantation in the P type trench and the N type trench to form a P type active region and an N type active region; and forming leads on the SOI substrate to complete the preparation of the solid-state plasma PiN diode. According to the embodiments, the high-performance solid-state plasma PiN diode, which is applicable to formation of a solid-state plasma antenna, can be prepared and provided through a deep trench isolation technology and an ion implantation process.

The invention discloses an ion filling and depositing combined treatment method of rolling bearing ring raceways. The method comprises the following steps: putting a to-be-treated rolling bearing ring into an ethanol solution with purity of 99%, and ultrasonically washing for one or more times with each for 15-20 minutes; putting the ultrasonically washed rolling bearing ring into the worktable of a vacuum chamber, mounting an Mo cathode at the pulse cathode arc source of the vacuum chamber, rotating the worktable to be in front of the pulse cathode arc source, and releasing a pulse bias voltage; introducing high-purity N2 into a vacuum chamber main body and releasing the pulse bias voltage; recovering the pressure of the vacuum chamber to be normal and cooling. After the inner and outer raceways of a rolling bearing are processed by adopting the method, the working surface hardness, wear resistance, corrosion resistance and fatigue resistance of the bearing are remarkably improved, the friction coefficient is remarkably reduced, and the service life of the bearing can be very effectively prolonged.

The invention relates to a planar PiN-type beta irradiation battery with a passivation layer surface field and a preparation method thereof, and the irradiation battery comprises a PiN unit and a radioactive isotope unit located on the PiN unit. The PiN unit comprises an N-type doped 4H-SiC substrate, an N-type doped 4H-SiC epitaxial layer, a P-type ion implantation region, an N-type ohmic contact electrode, a first passivation layer, a second passivation layer and a P-type ohmic contact electrode, and the P-type ion implantation region is located in the surface layer of the N-type doped 4H-SiC epitaxial layer to form a distributed P-type region; the first passivation layer is located on the N-type doped 4H-SiC epitaxial layer and covers the surface of an isolation mesa; the second passivation layer is located on the first passivation layer at the isolation mesa; the P-type ohmic contact electrode is located on the P-type ion implantation region, and the P-type ohmic contact electrode and the first passivation layer are arranged alternately. According to the irradiation battery, the energy deposition of beta rays in the P-type region is reduced, the short-circuit current Isc, the open-circuit voltage Voc and the fill factor FF are improved, and the purpose of improving the energy conversion efficiency of the beta irradiation battery is achieved.

A thyristor is disclosed, which comprises the following steps of manufacturing a thyristor: Ion in semiconductor substrate for P-Ions and N-Ion implantation, fabrication of P-trap, N-trap; S2, the junction of P-well and N-well is advanced by the first heating treatment; S3, then P-Ion implantation to fabricate P trap; S4, the second heating treatment is used to advance the P-well junction; S5, implanting N + ions and P + ions into two P traps and one N trap; S6, the third heating treatment activates the N + ion and the P + ion; 7, deep trench isolation is carry out on that semiconductor substrate. As such, that thyristor has a long service life, a simple manufacture method and a high manufacturing efficiency.